
MC68HC908GP32 MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
107
Chapter 11
FLASH Memory
11.1 Introduction
This section describes the operation of the embedded FLASH memory. This memory can be read,
programmed, and erased from a single external supply. The program, erase, and read operations are
enabled through the use of an internal charge pump.
11.2 Functional Description
The FLASH memory is an array of 32,256 bytes with an additional 36 bytes of user vectors and one byte
of block protection. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. Memory in
the FLASH array is organized into two rows per page basis. For the 32K word by 8-Bit Embedded FLASH
Memory, the page size is 128 bytes per page. Hence the minimum erase page size is 128 bytes. Program
and erase operation operations are facilitated through control bits in FLASH Control Register (FLCR).
Details for these operations appear later in this section. The address ranges for the user memory and
vectors are:
$8000–$FDFF; user memory.
$FF7E; FLASH block protect register.
$FE08; FLASH control register.
$FFDC–$FFFF; these locations are reserved for user-defined interrupt and reset vectors.
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.(1)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.