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Serial Peripheral Interface (SPI) Module
I/O Registers
MC68HC08GP32A MC68HC08GP16A
Data Sheet
MOTOROLA
Serial Peripheral Interface (SPI) Module
215
The SPI status and control register also contains bits that perform these functions:
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the shift
register to the receive data register. SPRF generates a CPU interrupt request if
the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status
and control register with SPRF set and then reading the SPI data register.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate CPU interrupt
requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte in the
receive data register before the next full byte enters the shift register. In an
overflow condition, the byte already in the receive data register is unaffected,
and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data
register. Reset clears the OVRF bit.
1 = Overflow
0 = No overflow
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during
a transmission with MODFEN set. In a master SPI, the MODF flag is set if the
SS pin goes low at any time with the MODFEN bit set. Clear MODF by reading
the SPI status and control register (SPSCR) with MODF set and then writing to
the SPI control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
Address: $0011
Bit 7
654321
Bit 0
Read:
SPRF
ERRIE
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
Write:
Reset:
00001000
= Unimplemented
Figure 16-15. SPI Status and Control Register (SPSCR)