參數(shù)資料
型號(hào)： MC68HC05J1
廠商： Motorola, Inc.
英文描述： HCMOS MICROCONTROLLER UNIT
中文描述： HCMOS微控制器
文件頁(yè)數(shù)： 34/82頁(yè)
文件大?。?/td> 327K
代理商： MC68HC05J1
MOTOROLA
5-4
RESETS AND INTERRUPTS
MC68HC705J2
Rev. 2
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The return from interrupt (RTI) instruction causes the CPU to recover the CPU
registers from the stack as shown in
Figure 5-2
.
5.2.1 Timer Interrupts
The timer generates two kinds of interrupts:
Timer overflow interrupt
Real-time interrupt
Setting the interrupt mask in the condition code register disables timer interrupts.
5.2.1.1 Timer Overflow Interrupts
A timer overflow interrupt occurs if the timer overflow flag, TOF, becomes set while
the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE are in the
timer control and status register. See
7.2 Timer Control and Status Register
(TCSR)
.
5.2.1.2 Real-Time Interrupts
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while
the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer
control and status register. See
7.2 Timer Control and Status Register (TCSR)
.
5.2.2 External Interrupt
When a falling edge occurs on theIRQ pin, an external interrupt request is latched.
When the CPU completes its current instruction, it tests the external interrupt latch.
If the interrupt latch is set and the interrupt mask in the condition code register is
reset, the CPU then begins the interrupt sequence. The CPU clears the interrupt
latch while it fetches the interrupt vector, so that another external interrupt request
can be latched during the interrupt service routine. As soon as the interrupt mask
is cleared (usually during the return from interrupt), the CPU can recognize the new
interrupt request.
Figure 5-3
shows the sequence of events caused by an interrupt.
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