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參數(shù)資料
| 型號(hào)： | MC68HC05F32CFU |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 196/198頁(yè) |
| 文件大?。?/td> | 2335K |
| 代理商： | MC68HC05F32CFU |
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MC68HC05F32
MOTOROLA
9-5
A/D CONVERTER
9
9.2.2
A/D result data register (ADDATA)
The A/D data register is a read-only register which is used to store the result of an A/D conversion.
The result is loaded into the register from the SAR and the conversion complete ag (COCO) in
the ADSCR register is set.
Caution: Performing a digital read of port D with levels other than VDD or VSS on the pins will
result in greater power dissipation during the read cycles.
9.3
A/D converter during WAIT mode
The A/D converter continues to operate normally during WAIT mode. To decrease power
consumption during WAIT, it is recommended that both the ADON and ADRC bits in the ADSTAT
register are cleared, if the A/D converter is not being used. If the A/D converter is being used and
the system clock frequency is above 1MHz, the ADRC bit should be cleared to disable the internal
RC oscillator.
9.4
A/D converter during STOP mode
In STOP mode the comparator and charge pump are turned off and the A/D converter ceases to
operate. Any pending conversion is aborted. When the clock begins oscillation upon leaving the
STOP mode, a nite amount of time passes before the A/D circuits stabilize enough to provide
conversions to the specied accuracy. Normally, the delays built into the MC68HC05F32 are
sufcient for this purpose, therefore no explicit delays need to be built into the software.
9.5
A/D analog input
The external analog voltage value to be processed by the A/D converter is sampled on an internal
capacitor through a resistive path, provided by input-selection switches and a sampling aperture
time switch, as shown in Figure 9-2. Sampling time is limited to 12 bus clock cycles. After sampling,
the analog value is stored on the capacitor and held until the end of conversion. During this hold
time, the analog input is disconnected from the internal A/D system and the external voltage
source sees a high impedance input.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
A/D data register
$004E
Undened
TPG
91
05F32Book Page 5 Tuesday, June 8, 1999 7:55 am
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| MC68HC705J1AVDWR2 | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HRC705J1ACDWR2 | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HSC705J1ACDWR2 | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HRC705J1ADWR2 | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05F32CPU | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32FU | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32PU | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F4 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:MECHANICAL DATA |
| MC68HC05F5 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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