參數(shù)資料
型號： MC68EN302CPV20BT
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù)： 13/128頁
文件大小： 641K
代理商： MC68EN302CPV20BT
xii
MC68EN302 USER’S MANUAL
MOTOROLA
LIST OF FIGURES
Figure
Title
Page
Number
Figure 1-1.
MC68EN302 Block Diagram ................................................................... 1-2
Figure 2-1.
Top Level Bus Structure.......................................................................... 2-1
Figure 2-2.
8-bit External to 16-bit Internal Read ...................................................... 2-8
Figure 2-3.
16-bit Internal to 8-bit External Write....................................................... 2-8
Figure 2-4.
Word Read with 3-Clock 8-Bit Accesses................................................. 2-9
Figure 2-5.
Word Write with 3-Clock 8-Bit Accesses................................................. 2-9
Figure 2-6.
Fast Cycle Word Read with –1 Wait State ............................................ 2-10
Figure 2-7.
Fast Cycle Word Write with -1 Wait State ............................................. 2-10
Figure 2-8.
External and Internal Interrupt Prioritization.......................................... 2-13
Figure 3-1.
Consecutive Four-Clock Accesses ........................................................ 3-4
Figure 3-2.
Five-Clock Accesses with Three-Clock Precharge ................................ 3-5
Figure 3-3.
Precharge With DRAM Access Active ................................................... 3-6
Figure 4-1.
Ethernet Controller Block Diagram.......................................................... 4-2
Figure 4-2.
Ethernet Receive Buffer D.0escriptor (Rx BD)...................................... 4-13
Figure 4-3.
Ethernet Transmit Buffer Descriptor (Tx BD) ........................................ 4-16
Figure 4-4.
Ethernet Address Recognition Flowchart.............................................. 4-25
Figure 4-5.
AR Memory Map - Perfect Match Mode................................................ 4-26
Figure 4-6.
AR Memory Map - Hash Mode.............................................................. 4-27
Figure 7-1.
Test Logic Block Diagram ....................................................................... 7-2
Figure 7-2.
TAP Controller State Machine................................................................. 7-3
Figure 7-3.
Output Latch Cell (iocell)......................................................................... 7-8
Figure 7-4.
Input Pin Cell (iscell) ............................................................................... 7-8
Figure 7-5.
Control Cell (dicell).................................................................................. 7-9
Figure 7-6.
Bidirectional Cell (bicell).......................................................................... 7-9
Figure 7-7.
Output Enable Cell (encell) ................................................................... 7-10
Figure 7-8.
Output Enable Cell (encello) ................................................................. 7-10
Figure 7-9.
Output Enable Cell (clko_encell)........................................................... 7-11
Figure 7-10. General Arrangement for Bidirectional Pins.......................................... 7-12
Figure 7-11. Bypass Register .................................................................................... 7-13
Figure 8-1.
DRAM Read Cycle .................................................................................. 8-3
Figure 8-2.
DRAM Write Cycle .................................................................................. 8-4
Figure 8-3.
DRAM Refresh ........................................................................................ 8-5
Figure 8-4.
Ethernet Collision Timing ........................................................................ 8-6
Figure 8-5.
Ethernet Receive Timing......................................................................... 8-6
Figure 8-6.
Ethernet Transmit Timing........................................................................ 8-6
Figure 8-7.
Test Clock Input Timing Diagram............................................................ 8-7
Figure 8-8.
TRST Timing Diagram ............................................................................ 8-7
Figure 8-9.
Boundary Scan (JTAG) Timing Diagram................................................. 8-8
Figure 8-10. Test Access Port Timing Diagram........................................................... 8-8
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