參數(shù)資料
型號： MC68334GVFC16
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 16 MHz, MICROCONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁數(shù)： 50/76頁
文件大小： 444K
代理商： MC68334GVFC16
MOTOROLA
MC68334
54
MC68334TS/D REV. 1
— = Not Implemented
Y = M111, where M represents the logic state of the MM bit in the SIMCR.
5.4 TPU Operation
All TPU functions are related to one of the two 16-bit free-running timebases. Functions are synthesized
by combining sequences of match events and capture events. Because the primitives are implemented
in hardware, the TPU can determine precisely when a match or capture event occurs, and respond rap-
idly. An event register for each channel provides for simultaneity of match/capture event occurrences
on all channels.
When a match or input capture event requiring service occurs, the affected channel generates a service
request to the scheduler. The scheduler determines the priority of the request and assigns the channel
to the microengine at the first available time. The microengine performs the function defined by the con-
tent of the control store or emulation RAM, using parameters from the parameter RAM.
5.4.1 Event Timing
Match and capture events are handled by independent channel hardware. This provides an event ac-
curacy of one time-base clock period, regardless of the number of channels that are active. An event
normally causes a channel to request service. However, before an event can be serviced, any pending
previous requests must be serviced. The time needed to respond to and service an event is determined
by the number of channels requesting service, the relative priorities of the channels requesting service,
and the microcode execution time of the active functions. Worst-case event service time (latency) de-
termines TPU performance in a given application. Latency can be closely estimated — see Motorola
TPU Reference Manual (TPURM/AD) for more information.
5.4.2 Channel Orthogonality
Most timer systems are limited by the fixed number of functions assigned to each pin. All TPU channels
contain identical hardware and are functionally equivalent in operation, so that any channel can be con-
figured to perform any time function. Any function can operate on the calling channel, and, under pro-
gram control, on another channel determined by the program or by a parameter. The user controls the
combination of time functions.
Table 26 TPU Parameter RAM Address Map
Channel
Base
Parameter Address
Number
Address
01234567
0
$YFFFF##
00
02
04
06
08
0A
—
1
$YFFFF##
10
12
14
16
18
1A
—
2
$YFFFF##
20
22
24
26
28
2A
—
3
$YFFFF##
30
32
34
36
38
3A
—
4
$YFFFF##
40
42
44
46
48
4A
—
5
$YFFFF##
50
52
54
56
58
5A
—
6
$YFFFF##
60
62
64
66
68
6A
—
7
$YFFFF##
70
72
74
76
78
7A
—
8
$YFFFF##
80
82
84
86
88
8A
—
9
$YFFFF##
90
92
94
96
98
9A
—
10
$YFFFF##
A0
A2
A4
A6
A8
AA
—
11
$YFFFF##
B0
B2
B4
B6
B8
BA
—
12
$YFFFF##
C0
C2
C4
C6
C8
CA
—
13
$YFFFF##
D0
D2
D4
D6
D8
DA
—
14
$YFFFF##
E0
E2
E4
E6
E8
EA
EC
EE
15
$YFFFF##
F0
F2
F4
F6
F8
FA
FC
FE
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