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| 型號： | MC68331CFC16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 33/84頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 16MHZ 132-PQFP |
| 標準包裝： | 36 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 18 |
| 程序存儲器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68331TS/D
39
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and
VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15
milliseconds. During this period, module port pins may be in an indeterminate state. While input-only
pins can be put in a known state by means of external pull-up resistors, external logic on input/output
or output-only pins must condition the lines during this time. Active drivers require high-impedance buff-
ers or isolation resistors to prevent conflict.
3.7.5 Use of Three State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,
high-impedance state. The signal must remain asserted for 10 clock cycles in order for drivers to
change state. There are certain constraints on use of TSC during power-on reset:
When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-
up time affects how long the 10 cycles take. Worst case is approximately 20 milliseconds from TSC
assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to high-imped-
ance state as soon after TSC assertion as 10 clock pulses have been applied to the EXTAL pin.
When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent
mode selection. Once the output drivers change state, the MCU must be powered down and re-
started before normal operation can resume.
3.8 Interrupts
Interrupt recognition and servicing involve complex interaction between the central processing unit, the
system integration module, and a device or module requesting interrupt service.
The CPU32 provides for eight levels of interrupt priority (0–7), seven automatic interrupt vectors and
200 assignable interrupt vector. All interrupts with priorities less than 7 can be masked by the interrupt
priority (IP) field in the status register. The CPU32 handles interrupts as a type of asynchronous excep-
tion.
Interrupt recognition is based on the states of interrupt request signals IRQ[7:1] and the IP mask value.
Each of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the
highest priority.
The IP field consists of three bits. Binary values %000 to %111 provide eight priority masks. Masks pre-
vent an interrupt request of a priority less than or equal to the mask value (except for IRQ7) from being
recognized and processed. When IP contains %000, no interrupt is masked. During exception process-
ing, the IP field is set to the priority of the interrupt being serviced.
Interrupt request signals can be asserted by external devices or by microcontroller modules. Request
lines are connected internally by means of a wired NOR — simultaneous requests of differing priority
can be made. Internal assertion of an interrupt request signal does not affect the logic state of the cor-
responding MCU pin.
External interrupt requests are routed to the CPU via the external bus interface and SIM interrupt control
logic. The CPU treats external interrupt requests as though they come from the SIM.
External IRQ[6:1] are active-low level-sensitive inputs. External IRQ7 is an active-low transition-sensi-
tive input. IRQ7 requires both an edge and a voltage level for validity.
IRQ[6:1] are maskable. IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive in order to prevent
redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is as-
serted, and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.
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| MC68331CFC16B1 | 功能描述:IC MCU 32BIT 16MHZ 132-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:M683xx 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標準包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68331CFC20 | 制造商:Freescale Semiconductor 功能描述: |
| MC68331CFC20B1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68331CFC25 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68331CFC25B1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
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