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MOTOROLA
M68040 USER’S MANUAL
xxi
LIST OF ILLUSTRATIONS (Continued)
Figure
Number
Page
Number
Title
B-10
B-11
B-12
Snoop Hit Timing..........................................................................................
Snoop Miss Timing.......................................................................................
Other Signal Timing .....................................................................................
B-19
B-20
B-21
C-1
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
C-10
C-11
C-12
C-13
C-14
C-15
C-16
C-17
C-18
C-19
C-20
C-21
MC68040V and MC68EC040V Functional Signal Groups...........................
MC68040V and MC68EC040V Initial Power-On Reset Timing ...................
MC68040V and MC68EC040V Normal Reset Timing..................................
MC68040V and MC68EC040V Test Logic Block Diagram ..........................
Bypass Register ...........................................................................................
Output Latch Cell (O.Latch) .........................................................................
Input Pin Cell (I.Pin) .....................................................................................
Output Control Cells (IO.Ctl) ........................................................................
General Arrangement of Bidirectional Pins..................................................
Circuit Disabling IEEE Standard 1149.1A ...................................................
Drive Levels and Test Points for AC Specifications .....................................
Clock Input Timing Diagram .........................................................................
Read/Write Timing........................................................................................
Bus Arbitration Timing..................................................................................
Snoop Hit Timing..........................................................................................
Snoop Miss Timing.......................................................................................
Other Signal Timing .....................................................................................
Going into LPSTOP with Arbitration.............................................................
LPSTOP no Arbitration, CPU is Master .......................................................
Exiting LPSTOP with Interrupt......................................................................
Exiting of LPSTOP with RESET...................................................................
C-3
C-8
C-9
C-11
C-13
C-14
C-14
C-15
C-15
C-17
C-18
C-21
C-24
C-25
C-26
C-27
C-28
C-29
C-30
C-31
C-31