
JTAG Timing
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
135
Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I2C Bus
10.13 JTAG Timing
Figure 10-15 Test Clock Input Timing Diagram
Table 10-18 JTAG Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
TCK frequency of operation1
1. TCK frequency of operation must be less than 1/8 the processor rate.
fOP
DC
SYS_CLK/8
MHz
TCK clock pulse width
tPW
50
—
ns
TMS, TDI data set-up time
tDS
5—
ns
TMS, TDI data hold time
tDH
5—
ns
TCK low to TDO data valid
tDV
—30
ns
TCK low to TDO tri-state
tTS
—30
ns
SDA
SCL
tHD; STA
tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA
SR
P
S
tHD; STA
tSP
tSU; STO
tBUF
tf
tr
tf
tr
TCK
(Input)
VM
VIL
VM = VIL + (VIH – VIL)/2
tPW
1/fOP
tPW
VM
VIH