參數(shù)資料
型號(hào)： MC56F8006VWL
廠商： Freescale Semiconductor
文件頁數(shù)： 57/106頁
文件大小： 0K
描述： DSC 16K FLASH 32MHZ 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲(chǔ)器容量： 16KB（8K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 16
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 15x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 734 (CN2011-ZH PDF)
配用： MC56F8006DEMO-ND - DEMO BOARD FOR MC56F8006
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor
54
8.9
Phase Locked Loop Timing
8.10
Relaxation Oscillator Timing
Table 25. Phase Locked Loop Timing
Characteristic
Symbol
Min
Typ
Max
Unit
PLL input reference frequency1
1 An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The
PLL is optimized for 8 MHz input.
fref
48
—
MHz
PLL output frequency2
2 The core system clock operates at 1/6 of the PLL output frequency.
fop
120
192
—
MHz
PLL lock time3 4
3 This is the time required after the PLL is enabled to ensure reliable operation.
4 From powerdown to powerup state at 32 MHz system clock state.
tplls
—40
100
s
Accumulated jitter using an 8 MHz external crystal as the PLL source5
5 This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 32 MHz system clock
frequency and using an 8 MHz oscillator frequency.
JA
—
0.37
%
Cycle-to-cycle jitter
tjitterpll
—350
—
ps
Table 26. Relaxation Oscillator Timing
Characteristic
Symbol Minimum Typical
Maximum
Unit
Relaxation oscillator output frequency1
Normal Mode
Standby Mode
1 Output frequency after factory trim.
fop
—
8.05
400
—
MHz
kHz
Relaxation oscillator stabilization time2
2 This is the time required from standby to normal mode transition.
troscs
—1
3
ms
Cycle-to-cycle jitter. This is measured on the CLKO signal
(programmed prescaler_clock) over 264 clocks3
3 J
A is required to meet QSCI requirements.
tjitterrosc
—400
—
ps
Variation over temperature –40
C to 105 C4
4 See Figure 22. The power supply VDD must be greater than or equal to 2.6 V. Below 2.6 V, the maximum variation
over the whole temperature and whole voltage range from 1.8 V to 2.6 V will be +/-16%.
—
–3.0 to +2.0
%
Variation over temperature 0
C to 105 C5
5 This data is only applied to devices with temperature range from –40
C to 105 C.
—
–2.0 to +2.0
%
Variation over temperature –40
C to 125 C4
—
–3.5 to +3.0
%
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參數(shù)描述
MC56F8006VWL 制造商:Freescale Semiconductor 功能描述:IC DSC 16BIT 16KB 32MHZ 3.6V SOIC-28
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MC56F8011 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
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MC56F8013 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
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