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參數(shù)資料
| 型號(hào)： | MC54HC541AJ |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver |
| 中文描述： | HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | MC54HC541AJ |
MC54/74HC541A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
DC CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
V
Symbol
Unit
≤
125
°
C
≤
85
°
C
–55 to 25
°
C
VCC
Condition
Parameter
Iin
IOZ
Maximum Input Leakage Current
Vin = VCC or GND
Output in High Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±
0.1
±
1.0
±
1.0
μ
A
Maximum Three–State Leakage
Current
6.0
±
0.5
±
5.0
±
10.0
μ
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
μ
A
6.0
4
40
160
μ
A
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
V
Guaranteed Limit
Symbol
Parameter
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
Cin
Cout
Maximum Input Capacitance
10
10
10
pF
Maximum Three–State Output Capacitance (Output in High
Impedance State)
15
15
15
pF
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V, VEE = 0 V
35
pF
Figure 1.
VCC
GND
INPUT A
OUTPUT Y
tPLH
OE1 or OE2
50%
VCC
GND
OUTPUT Y
tPZL
OUTPUT Y
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
tPHL
90%
50%
10%
tr
tTLH
tf
tTHL
Figure 2.
SWITCHING WAVEFORMS
90%
50%
10%
50%
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