參數(shù)資料
型號(hào)： MC44BS373CAEF
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 4/52頁(yè)
文件大小： 0K
描述： AUDIO VIDEO INTERGRATION MOD
標(biāo)準(zhǔn)包裝： 48
類型： NTSC/PAL 調(diào)制器
應(yīng)用： 音頻/視頻，VCR，機(jī)頂盒
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
MC44BS373CA Data Sheet
I2C Programming
Table 18 lists settings of fields X5, X4, and X3, used to set the device into test mode 2.
Table 19 lists settings of fields Y2, Y1, and OOR, used to set the device into READ mode and to determine
RF oscillator out-of-frequency range information.
1
0
1
1.f
DC drive applied to modulators—Non-inverted video at TVOUT
1
0
1.g
DC drive applied to modulators—Inverted video at TVOUT
1
1.h
Transient output inhibit disabled (that is, speed-up mode)
During this speed-up test mode, ATT = 0 forces sound current source to 1
A,
while ATT = 1 forces it to 10
A.
Table 18. Write Mode—Test Mode 2
X5
X4
X3
State
Description
0
2.a
Normal operation
0
1
2.b
Test pattern generator DC verification (test pattern DC test mode available)
0
1
0
2.c
Program divider test (UHF program divider on PLLFILT pin and sound program
divider on SPLLFIL pin)
0
1
2.d
Reference divider test (UHF reference divider on PLLFILT pin)
1
0
2.e
UHF phase comparison, upper source on PLLFILT pin
Sound phase comparison 10-
A upper source on SPLLFIL
(only valid during transient output inhibit)
1
0
1
2.f
UHF phase comparison, lower source on PLLFILT pin
Sound phase comparison 10-
A lower source on SPLLFIL
(only valid during transient output inhibit)
1
0
2.g
Sound phase comparison 1-
A upper source on SPLLFIL
(not valid during transient output inhibit)
1
2.h
Sound phase comparison 1-
A lower source on SPLLFIL
(not valid during transient output inhibit)
Table 19. Read Mode
Bit
Value
Setting
OOR
0
Normal operation, VCO in range
1
VCO out of range
Y1
0
VCO out of range, frequency too low. Only valid if OOR=1
1
VCO out of range, frequency too high. Only valid if OOR=1
Y2
0
High VCO is active.
1
Low VCO is active.
Table 17. Write Mode—Test Mode 1 and VHF Range (continued)
X2
X1
X0
State
Description
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