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參數(shù)資料
| 型號： | MC44725VFU |
| 廠商： | Motorola, Inc. |
| 英文描述： | Digital Video Encoder |
| 中文描述： | 數(shù)字視頻編碼器 |
| 文件頁數(shù)： | 5/39頁 |
| 文件大?。?/td> | 518K |
| 代理商： | MC44725VFU |
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MC44724/5 Rev 0.21 03/25/97
No.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
5
Clock
27.0Mhz is necessary. This signal on the clock pin needs to be active before the reset pin is de-asserted.
( see figures 1 and 2 )
[Function Descriptions]
Fig 1 : DVIN Data Input Timing
Input Clock 27MHz
Input Data
DVIN0~7
50%
Tds
Tdh
Clock 27MHz
Output data
H/VF sync
Output Data
TP0~8
Td
Td
Fig 2 : Sync Data Output Timing
Reset Procedure
RESET is a level sensitive input pin. Driving the RESET pin low causes a DVE reset. The 27Mhz DVE
clock signal must be active before RESET is released. De-asserting reset will latch the status of the PAL/
NTSC, TVIN and SEL pins.
The PAL/NTSC pin determines the default values for the DVE control registers. The default register
values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately
when a valid input digital video data stream is present.
The value on the SEL pins determine the default serial communication mode. If Low, the DVE use I2C bus
operation. If High, the DVE use 4-wired SPI operation.
After reset, the VBI signals (Closed-Caption, CGMS and WSS ) are disabled.
(see page --- for sub-address register descriptions.)
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