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參數(shù)資料
| 型號(hào)： | MC44724 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Digital Video Encoder |
| 中文描述： | 數(shù)字視頻編碼器 |
| 文件頁數(shù)： | 6/39頁 |
| 文件大?。?/td> | 518K |
| 代理商： | MC44724 |
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MC44724/5 Rev 0.21 03/25/97
No.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Video Timing / Sync Generator
The DVE outputs PAL-B,D,G,H,I, PAL-N, PAL-M or NTSC-M standard video signals.
The DVE sync generator can be operated in two modes, master or slave.
In master mode, the DVE generates all the correct Horizontal and Vertical or Frame sync signals
internally, or it is output Csync signal through the EXT pin(C/Fsync).
In slave mode, the DVE derives the sync signals from the Bit-Parallel input data stream Start Active
Video (SAV) and End Active Video (EAV) data packet information. Sync signals are output on the
Hsync and F/Vsync or EXT pins and can be programmed for positive or negative polarity. The phase of
Hsync can also be controlled.
Also, the DVE allows more two slave modes. One is H/Vsync slave, and the aother is H/Fsync slave
mode.
Vertical Blanking corresponds to the following lines.
625/50 624-22 311-335 ITU-R line numbering
525/60 1-19 264-282 SMPTE line numbering
(see figures 3,4,5,6,7,8,9,10, and 11 for sub-address register descriptions.)
Input Data Format
The input digital video is in accord with the ITU-R Rec.656 and SMPTE 125M standards. It is an two 8-bit
or 16-bit multiplexed 4:2:2 ((CB,Y,CR)Y) data stream. Samples are latched on the rising edge of the clock
signal. Data is input on pins
DVIN[ 7 : 0 ]
and
TP[ 8 : 1 ]
(see figures 3 and 4 for sub-address register descriptions.)
6
Fig 3 : Digital Input Timing(525/60 system) in Master Mode
70(hex){[1:0]=01}
1440T
Hsync phase
sub-address71[2:0]
+4T delay
Hsync
clock
128T
T
244T
Hsync polarity
sub-address71[5]
-3T delay
DVIN0~7
Cr
718
Cb
718
Y
718
Y
719
00
00
FF
Cb
2
Cr
0
Cb
0
Y
0
Y
1
Y
2
INVALID
00
00
XY
FF
Y
718
Y
719
TP1~8
Cr
718
Cb
718
Cb
2
Cr
0
Cb
0
INVALID
DVIN0~7
Y2
Y
1
Y
0
INVALID
16-bit input mode
8-bit input mode
Cb
718
Cr
718
Cr
2
Cr
0
Cb
0
or
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