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參數(shù)資料
| 型號： | MC44145D |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | PIXEL CLOCK GENERATOR/ SYNC SEPARATOR |
| 中文描述： | 42 MHz, VIDEO CLOCK GENERATOR, PDSO14 |
| 封裝： | PLASTIC, SOP-14 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 98K |
| 代理商： | MC44145D |
MC44145
7
MOTOROLA ANALOG IC DEVICE DATA
LOOP FILTER CALCULATION
This section is not intended as a complete loop theory; its
aim is merely to point out the peculiarities of the loop, and
provide the user with enough information for the filter
components selection. For a more in–depth covering, the
cited reference should be consulted, especially [1].
The following remarks apply to the loop:
The loop frequency is 15 kHz.
In spite of the sampled nature of the loop, a continuous
time approximation is possible if the loop bandwidth is
sufficiently small.
Ripple on VC is a function of the loop bandwidth
The loop is a type II, 3rd order; however, since C2 is
small, the pole it creates is far removed from the low
frequency dominant poles, and the loop can be analyzed
as a 2nd order loop.
These remarks apply to the PFD:
Phase and frequency sensitive.
Independent of duty cycle.
PFD has 3 allowed states: up, down, hi–Z
The VCO is always pulled in the right direction (during
acquisition).
PFD gain is higher near lock.
The last two remarks imply that only the higher value need
be taken into account, as acquisition will be slower, but
always in the proper direction, whereas the higher gain will
enter the action as soon as the error reaches
±
2
π
.
The following values are selected and defined (see Block
Diagram):
C2 = C/10 or less, to satisfy the requirement that the effect
of C2 on the low frequency response of the loop be minimal,
and similar to a second order loop.
ζ
= 0.707 for the damping factor.
ω
i = 15625 x 2
π
the input pulsation.
τ
= RC as the loop filter.
Κ
=
Κ
o x
Ι
p x R/(2 x
π
x N) the loop gain.
Κ
′
=
Κ
x
τ
= 4
ζ
2 is the “normalized” loop gain.
Κ
o = 57 x 106 [rad/Vs] (9.0 MHz/V).
Stability analysis, with C2 = C/10 and
Κ
′
= 2 (
ζ
= 0.707)
gives a minimum value of 7.5 for the ratio
ω
i/
Κ
and to have
some margin, a reasonable value can be 15 to 20 or higher [1].
Selecting
ω
i/
Κ
= 20, gives :
Κ
=
ω
i/20
≈
5000.
With
Κ
′
= 2,
τ
= 2/
Κ
= 400
μ
s.
Using
Κ
=
Κ
o x
Ι
p x R/(2 x
π
x N) and setting
Ι
p = 60
μ
A,
and N an average value of 1000, we get R = 9.1 k
.
Then for
τ
= 400
μ
s, C becomes 47 nF and C2, 4.7 nF.
With these values, the loop natural frequency (
ω
n) and the
loop bandwidth (
ω
3dB) can be calculated:
ω
n = [(
Κ
o/N) x
Ι
p/(2
π
C)1/2 = 3400 and
fn = 3400/2
π
= 540 Hz.
ω
3dB = 2 x
ω
n = 1080 Hz (valid if
ζ
is close to 0.707).
References:
[1] Charge–Pump Phase–Lock Loops, Floyd M. Gardner,
IEEE transactions on communications, vol. com–28
no. 11 November 1980
[2] Phaselock Techniques, Floyd M. Gardner, J. Wiley &
Sons, 1979
[3] Phase–Locked Loops, Roland E. Best, McGraw–Hill,
1984
[4] Phase–Locked Loop Systems, Motorola
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