LOGIC COMMANDS AND REGISTERS ARCHIVE INFORMA" />
參數(shù)資料
型號： MC33993DWB
廠商： Freescale Semiconductor
文件頁數(shù)： 8/28頁
文件大?。?/td> 0K
描述： IC SWITCH I/O INTERFACE 32-SOIC
標(biāo)準(zhǔn)包裝： 42
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 32-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 32-SOIC
包裝： 管件
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
33993
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
ARCHIVE
INFORMATION
ARCHIVE
INFORMATION
SPI COMMAND SUMMARY
Table 14 below provides a comprehensive list of SPI
commands recognized by the 33993 and the reset state of
each register. Table 15 and Table 16 contain the Serial
Output (SO) data for input voltages greater or less than the
threshold level. Open switches are always indicated with a
logic [0], closed switches are indicated with logic [1].
Table 14. SPI Command Summary
MSB
Command Bits
Setting Bits
LSBI
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Switch Status
Command
0
X
Settings Command
Bat=1, Gnd=0
(Default state = 1)
0
1
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Wake-Up/Interrupt
Bit
Wake-Up=1
Nonwake-Up=0
(Default state = 1)
0
1
0
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
1
X
SG1
3
SG1
2
SG1
1
SG1
0
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Metallic Command
Metallic = 1
Non-metallic = 0
(Default state = 1)
0
1
0
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
1
0
1
X
SG1
3
SG1
2
SG1
1
SG1
0
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Analog Command
0
1
0
X
16m
A
0
2.0m
A
0
Wetting Current
Timer
Enable Command
Timer ON = 1
Timer OFF = 0
(Default state = 1)
0
1
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
1
0
X
SG1
3
SG1
2
SG1
1
SG1
0
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Tri-State Command
Input Tri-State=1
Input Active = 0
(Default state = 1)
0
1
0
1
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
1
0
1
0
X
SG1
3
SG1
2
SG1
1
SG1
0
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Calibration
Command
(Default state -
uncalibrated)
0
1
0
1
X
Sleep Command
0
1
0
X
int
timer
int
timer
int
timer
scan
timer
scan
timer
scan
timer
Reset Command
0
1
X
SO Response Will
Always Send
them
flg
int
flg
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG1
3
SG1
2
SG1
1
SG1
0
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
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