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參數(shù)資料
| 型號： | MC33972EW |
| 廠商： | Motorola, Inc. |
| 英文描述： | Multiple Switch Detection Interface with Suppressed Wake-Up |
| 中文描述： | 多交換檢測接口，具有抑制喚醒 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 506K |
| 代理商： | MC33972EW |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33972
9
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33972 device is an integrated circuit designed to provide
systems with ultra-low quiescent sleep/wake-up modes and a
robust interface between switch contacts and a
microprocessor. The 33972 replaces many of the discrete
components required when interfacing to microprocessor-
based systems while providing switch ground offset protection,
contact wetting current, and system wake-up.
The 33972 features 8-programmable switch-to-ground or
switch-to-battery inputs and 14 switch-to-ground inputs. All
switch inputs may be read as analog inputs through the analog
multiplexer (AMUX). Other features include a programmable
wake-up timer, programmable interrupt timer, programmable
wake-up/interrupt bits, and programmable wetting current
settings.
This device is designed primarily for automotive applications
but may be used in a variety of other applications such as
computer, telecommunications, and industrial controls.
FUNCTIONAL TERMINAL DESCRIPTION
CS
The system MCU selects the 33972 to receive
communication using the chip select (
CS
) terminal. With the
CS
in a logic LOW state, command words may be sent to the 33972
via the serial input (SI) terminal, and switch status information
can be received by the MCU via the serial output (SO) terminal.
The falling edge of
CS
enables the SO output, latches the state
of the
INT
terminal, and the state of the external switch inputs.
Rising edge of the
CS
initiates the following operation:
1. Disables the SO driver (high impedance)
2.
INT
terminal is reset to logic [1], except when additional
switch changes occur during
CS
LOW. (See
Figure 4
on
page 8.)
3. Activates the received command word, allowing the
33972 to act upon new data from switch inputs.
To avoid any spurious data, it is essential the HIGH-to-LOW
and LOW-to-HIGH transitions of the
CS
signal occur only when
SCLK is in a logic LOW state. Internal to the 33972 device is an
active pullup to V
DD
on
CS
.
In Sleep mode the negative edge of
CS
(V
DD
applied) will
wake up the 33972 device. Data received from the device
during
CS
wake-up may not be accurate.
SCLK
The system clock (SCLK) terminal clocks the internal shift
register of the 33972. The SI data is latched into the input shift
register on the falling edge of SCLK signal. The SO terminal
shifts the switch status bits out on the rising edge of SCLK. The
SO data is available for the MCU to read on the falling edge of
SCLK. False clocking of the shift register must be avoided to
ensure validity of data. It is essential the SCLK terminal be in a
logic LOW state whenever
CS
makes any transition. For this
reason, it is recommended, though not necessary, that the
SCLK terminal is commanded to a logic LOW state as long as
the device is not accessed and
CS
is in a logic HIGH state.
When the
CS
is in a logic HIGH state, any signal on the SCLK
and SI terminals will be ignored and the SO terminal is tri-state.
SI
The SI terminal is used for serial instruction data input. SI
information is latched into the input register on the falling edge
of SCLK. A logic HIGH state present on SI will program a
one
in the command word on the rising edge of the
CS
signal. To
program a complete word, 24 bits of information must be
entered into the device.
SO
The SO terminal is the output from the shift register. The SO
terminal remains tri-stated until the
CS
terminal transitions to a
logic LOW state. All
open switches
are reported as
zero
, all
closed switches
are reported as
one
. The negative transition of
CS
enables the SO driver.
The first positive transition of SCLK will make the status data
bit 24 available on the SO terminal. Each successive positive
clock will make the next status data bit available for the MCU to
read on the falling edge of SCLK. The SI/SO shifting of the data
follows a first-in, first-out protocol, with both input and output
words transferring the most significant bit (MSB) first.
INT
The
INT
terminal is an interrupt output from the 33972
device. The
INT
terminal is an open-drain output with an internal
pullup to V
DD
. In Normal mode, a switch state change will trigger
the
INT
terminal (when enabled). The
INT
terminal and INT bit
in the SPI register are latched on the falling edge of
CS
. This
permits the MCU to determine the origin of the interrupt. When
two 33972 devices are used, only the device initiating the
interrupt will have the INT bit set. The
INT
terminal is cleared on
the rising edge of
CS
. The
INT
terminal will not clear with rising
edge of
CS
if a switch contact change has occurred while
CS
was LOW.
In a multiple 33972 device system with
WAKE
HIGH and V
DD
on (Sleep mode), the falling edge of
INT
will place all 33972s in
Normal mode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| MC33972EWR2 | 功能描述:多路器開關(guān) IC MSDISW RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關(guān)閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| MC33972TEW | 功能描述:接口 - 專用 MULTI-SW DETECT W/SUPRES RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| MC33972TEWR2 | 功能描述:接口 - 專用 MULTI-SW DETECT W/SUPRES RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| MC33975ATEK | 功能描述:接口 - 專用 ENHANCED MULTI SW DETECT RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| MC33975ATEKR2 | 功能描述:接口 - 專用 ENHANCED MULTI SW DETECT RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
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