LOGIC COMMANDS AND REGISTERS Figure 30. HS " />
參數(shù)資料
型號(hào)： MC33742SDWR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 50/71頁(yè)
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/LIN 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 自動(dòng)
接口： SPI
電源電壓： 5.5 V ~ 18 V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
安裝類(lèi)型： 表面貼裝
配用： KIT33742DWEVB-ND - KIT FOR 33742 SBC WITH EHSCAN
Analog Integrated Circuit Device Data
54
Freescale Semiconductor
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 30. HS Operation When Cyclic Sense Is Selected
LOW POWER CONTROL REGISTER (LPC)
Tables 36 through 40 contain the Low Power Control Register information. The LPC register controls:
The state of HS in Stop and Sleep modes (HS permanently OFF or HS cyclic).
Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is
defined by the TIM2 sub register).
Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to
Reset Control Register (RCR) on page 49 for details of the LPC register setup required for proper cyclic sense or direct wake-
up operation.
The LPC register also reports the CANH and RXD diagnostic.
Table 34. TIM2 Timing and CANL Failure Diagnostic Register
TIM2
R/W
D3
D2
D1
D0
$101b
W
1
CSP2
CSP1
CSP0
R
CANL2VDD
CANL2BAT
CANL2GND
TXPD
Reset Value
–
0
Reset Condition (Write)(64)
–
POR, RESET
Notes
64.
See Table 13, page 46, for definitions of reset conditions.
Table 35. TIM2 Control Bits
CSP2
CSP1
CSP0
Cyclic Sense Timing (ms)
Parameter
0
4.6
Cyclic Sense/FWU Timing 1
0
1
9.25
Cyclic Sense/FWU Timing 2
0
1
0
18.5
Cyclic Sense/FWU Timing 3
0
1
37
Cyclic Sense/FWU Timing 4
1
0
74
Cyclic Sense/FWU Timing 5
1
0
1
95.5
Cyclic Sense/FWU Timing 6
1
0
191
Cyclic Sense/FWU Timing 7
1
388
Cyclic Sense/FWU Timing 8
Cyclic Sense Timing, OFF Time
time
HS
Sample
10
s
HS OFF
HS ON
Lx Sampling Point
Cyclic Sense Timing,
ON Time
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