參數(shù)資料
型號(hào)： MC33260PG
廠商： ON SEMICONDUCTOR
元件分類(lèi)： 穩(wěn)壓器
英文描述： GreenLine TM Compact Power Factor Controller: Innovative Circuit for Cost Effective Solutions
中文描述： 0.5 A POWER FACTOR CONTROLLER, PDIP8
封裝： LEAD FREE, PLASTIC, DIP-8
文件頁(yè)數(shù)： 13/22頁(yè)
文件大?。?/td> 232K
代理商： MC33260PG
MC33260
http://onsemi.com
13
Pin Numbers are Relevant to the PDIP8 Version
In particular, a 11 V Zener diode is internally connected
between the terminal and ground on the following pins:
Feedback, V
control
, Oscillator, Current Sense, and
Synchronization.
Figure 31. Synchronization Arrangement
S2
R2
Q2
S1
R2
Q1
&
2 s
R
sync
+
Sync
5
1 V
UVLO
1 V
Output_Ctrl
PWM
Latch
Set
Q1 High <=>
Synchronization Mode
SYNCHRONIZATION BLOCK
The MC33260 features two modes of operation:
Free Running Discontinuous Mode: The power switch
is turned on as soon as there is no current left in the
inductor (Zero Current Detection). This mode is
simply obtained by grounding the synchronization
terminal (Pin 5).
Synchronization Mode: This mode is set as soon as a
signal crossing the 1.0 V threshold, is applied to the
Pin 5. In this case, operation in free running can only
be recovered after a new circuit startup. In this mode,
the power switch cannot turn on before the two
following conditions are fulfilled.
Still, the zero current must have been detected.
The precedent turn on must have been followed by
(at least) one synchronization raising edge
crossing the 1.0 V threshold.
In other words, the synchronization acts to prolong the
power switch off time.
Consequently, a proper synchronized operation requires
that the current cycle (ontime + inductor demagnetization)
is shorter than the synchronization period. Practically, the
inductor must be chosen accordingly. Otherwise, the system
will keep working in free running discontinuous mode.
Figure 36 illustrates this behavior.
It must be noticed that whatever the mode is, a 2.0 s
minimum offtime is forced. This delay limits the switching
frequency in light load conditions.
OUTPUT SECTION
The output stage contains a totem pole optimized to
minimize the cross conduction current during high speed
operation. The gate drive is kept in a sinking mode whenever
the Undervoltage Lockout is active. The rise and fall times
have been controlled to typically equal 50 ns while loaded
by 1.0 nF.
REFERENCE SECTION
An internal reference current source (I
ref
) is trimmed to be
±
4% accurate over the temperature range (the typical value
is 200 A). I
ref
is the reference used for the regulation
(I
regH
= I
ref
).
UNDERVOLTAGE LOCKOUT SECTION
An Undervoltage Lockout comparator has been
implemented to guarantee that the integrated circuit is
operating only if its supply voltage (V
CC
) is high enough to
enable a proper working. The UVLO comparator monitors
the Pin 8 voltage and when it exceeds 11 V, the device gets
active. To prevent erratic operation as the threshold is
crossed, 2.5 V of hysteresis is provided.
The circuit off state consumption is very low: in the range
of 100 A @ V
CC
= 5.0 V. This consumption varies versus
V
CC
as the circuit presents a resistive load in this mode.
THERMAL SHUTDOWN
An internal thermal circuitry is provided to disable the
circuit gate drive and then to prevent it from oscillating, if
the junction temperature exceeds 150
°
C typically.
The output stage is again enabled when the temperature
drops below 120
°
C typically (30
°
C hysteresis).
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