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參數(shù)資料
| 型號： | MC2GH256NMCA-2SA00 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | SAMSUNG MultiMediaCard |
| 中文描述： | 三星多媒體 |
| 文件頁數(shù)： | 86/102頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | MC2GH256NMCA-2SA00 |
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MultiMediaCard
TM
86
Sep.22.2005
Revision 0.3
7.10 Read CID/CSD Registers
Unlike the MultiMediaCard protocol (where the register contents is sent as a command response), reading the contents of
the CSD and CID registers in SPI mode is a simple read-block transaction. The card will respond with a standard response
token (see Figure ) followed by a data block of 16 bytes suffixed with a 16 bit CRC.
The data time out for the CSD command cannot be set to the card TAAC since this value is stored in the CSD.
Refer to Section 7.23.2 for detailed timing. For consistency, read CID transaction is identical to read CSD.
7.11 Reset Sequence
The MultiMediaCard requires a defined reset sequence. After power on reset or CMD0 (software reset) the card enters an
idle state. At this state the only legal host commands are CMD1 (SEND_OP_COND) and CMD58 (READ_OCR).
The host must poll the card (by repeatedly sending CMD1) until the ‘in-idle-state’ bit in the card response indicates (by
being set to 0) that the card has completed its initialization processes and is ready for the next command.
In SPI mode, as opposed to MultiMediaCard mode, CMD1 has no operands and does not return the contents of the OCR
register. Instead, the host may use CMD58 (available in SPI mode only) to read the OCR register. Furthermore, it is in the
responsibility of the host to refrain from accessing a card that does not support its voltage range.
The usage of CMD58 is not restricted to the initializing phase only, but can be issued at any time. The host must poll the
card (by repeatedly sending CMD1) until the ‘in-idle-state’ bit in the card response indicates (by being set to 0) that the
card has completed its initialization processes and is ready for the next command.
7.12 Clock Control
The SPI bus clock signal can be used by the SPI host to put the card into energy saving mode or to control the data flow
(to avoid under-run or over-run conditions) on the bus. The host is allowed to change the clock frequency or shut it down.
There are a few restrictions the SPI host must follow:
The bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency, defined by
the MultiMediaCards)
It is an obvious requirement that the clock must be running for the MultiMediaCard to output data or response tokens.
After the last SPI bus transaction, the host is required, to provide 8 (eight) clock cycles for the card to complete the opera-
tion before shutting down the clock. throughout this 8 clocks period the state of the CS signal is irrelevant. it can be
asserted or de-asserted.
Following is a list of the various SPI bus transactions:
A command / response sequence. 8 clocks after the card response end bit. The CS signal can be asserted or de-
asserted during these 8 clocks.
A read data transaction. 8 clocks after the end bit of the last data block.
A write data transaction. 8 clocks after the CRC status token.
The host is allowed to shut down the clock of a “busy” card. The MultiMediaCard will complete the programming opera-
tion regardless of the host clock. However, the host must provide a clock edge for the card to turn off its busy signal. With-
out a clock edge the MultiMediaCard (unless previously disconnected by de-asserting the CS signal) will force the dataOut
line down, permanently.
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| MC2M | 制造商:G & J HALL 功能描述:STEP DRILL 10-20MM 1MM STEP 制造商:G & J HALL 功能描述:STEP DRILL, 10-20MM, 1MM STEP 制造商:G & J HALL 功能描述:STEP DRILL, 10-20MM, 1MM STEP; Drill Bit Size Metric:10mm; Overall Length:77.5mm; SVHC:No SVHC (19-Dec-2012); Drill Bit Type:Step; Material:Steel; Material Thickness Max:4mm; Range:10mm - 20mm; Range:10mm - 20mm; Shank Dia:9mm; ;RoHS Compliant: NA |
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