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參數(shù)資料
| 型號： | MC1494P |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | OC-48/24/12/3 SONET SDH Multi-Rate Transceiver with Enhanced Jitter Tolerance 100-HTQFP -40 to 85 |
| 中文描述： | ANALOG MULTIPLIER OR DIVIDER, 0.8 MHz BAND WIDTH, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 319K |
| 代理商： | MC1494P |
MC1494
10
MOTOROLA ANALOG IC DEVICE DATA
–V2
10
9
10
+
+
15
5
14
2
3
–
+
11
12
30 k
62 k
7
8
+15 V –15 V
P4
50 k
22 k
10 pF
MC1456
–15 V
+15 V
4
7
10 pF
510
V
+
MC1494
1
3
6
13
4
2
16 k
51 k
20 k
P1
20 k
Input
Offset
P3
Output
Offset
6
VO =
Figure 21. MC1494 Squaring Circuit
This shows that all error terms can be eliminated with only
three adjustment potentiometers, eliminating one of the input
offset adjustments. For instance, if the “X” input offset
adjustment is eliminated,
∈
x is determined by the internal
offset (Viox) but
∈
y is adjustable to the extent that the (
∈
x+
∈
y)
term can be zeroed. Then the output offset adjustment is
used to adjust the Voo term and thus zero the remaining error
terms. An AC procedure for nulling with three adjustments is:
A.
AC Procedure:
1. Connect oscillator (1.0 kHz, 15 Vpp) to input.
2. Monitor output at 2.0 kHz with tuned voltmeter and
adjust P4 for desired gain ( Be sure to peak
response of voltmeter).
3. Tune voltmeter to 1.0 kHz and adjust P1 for a minimum
output voltage.
4. Ground input and adjust P3 (output offset) for
0 Vdc out.
5. Repeat steps 1 through 4 as necessary.
B.
DC Procedure:
1. Set VX = VY = 0 V and adjust P3 (output offset
potentiometer) such that VO = 0 Vdc.
2. Set VX = VY = 1.0 V and adjust P1 (Y input offset
potentiometer) such that the output voltage is
– 0.100 V.
3. Set VX = VY = 10 Vdc and adjust P4 (load resistor)
such that the output voltage is –10 V.
4. Set VX = VY = –10 Vdc and check that VO = –10 V.
5. Repeat steps 1 through 4 as necessary.
Divide
Divide circuits warrant a special discussion as a result of
their special problems. Classic feedback theory teaches that
if a multiplier is used as a feedback element in an operational
amplifier circuit, the divide function results. Figure 22
illustrates the theoretical simplicity of such an approach and
a practical realization is shown in Figure 23.
The characteristic “failure” mode of the divide circuit is
latch–up. One way it can occur is if VX is allowed to go
negative, or in some cases, if VX approaches zero.
Figure 22 illustrates why this is so. For VX > 0 the transfer
function through the multiplier is noninverting. Its output is fed
to the inverting input of the op amp Thus, operation is in the
negative feedback mode and the circuit is DC stable.
Figure 22. Basic Divide Circuit Using Multiplier
+
+
+
+
–
VZ
–
KVX VY
VX
MC1494
VO
VZ = –KVXVY
or
VO =
–VZ
KVX
+
VY
Should VX change polarity, the transfer function through
the multiplier becomes inverting, the amplifier has positive
feedback and latch–up results. The problem resulting from
VX being near zero is a result of the transfer through the
multiplier being near zero. The op amp is then operating with
a very high closed–loop gain and error voltages can thus
become effective in causing latch–up.
The other mode of latch–up results from the output voltage
of the op amp exceeding the rated common mode input
voltage of the multiplier. The input stage of the multiplier
becomes saturated, phase reversal results, and the circuit is
latched up. The circuit of Figure 23 protects against this
happening by clamping the output swing of the op amp to
approximately
±
10.7 V. Five percent tolerance, 10 V zeners
are used to assure adequate output swing but still limit the
output voltage of the op amp from exceeding the common
mode input range of the MC1494.
Setting up the divide circuit for reasonably accurate
operation is somewhat different from the procedure for the
multiplier itself. One approach, however, is to break the
feedback loop, null out the multiplier circuit, and then close
the loop.
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