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參數(shù)資料
| 型號： | MC14597B |
| 廠商： | Motorola, Inc. |
| 英文描述： | Battery-Backup Supervisor for Low Power Processors 14-TSSOP -40 to 85 |
| 中文描述： | 8位總線兼容鎖存 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 262K |
| 代理商： | MC14597B |
MOTOROLA CMOS LOGIC DATA
MC14597B MC14598B
2
VDD
Vin
Vin
DC Supply Voltage
– 0.5 to + 18.0
V
Input Voltage, Enable (DC or Transient)
– 0.5 to VDD + 0.5
– 0.5 to VDD + 12
V
Input Voltage, All other Inputs
(DC or Transient)
V
Vout
Iin, lout
Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
±
10
V
Input or Output Current (DC or Transient),
per Pin
mA
PD
Tstg
TL
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Min
Output Voltage
“0” Level
Vin = VDD or 0
10
15
—
“1” Level
Vin = 0 or VDD
10
15
14.95
Vdc
Characteristic
Symbol
VOL
Typ #
0
0
0
5.0
10
15
Unit
Vdc
Max
0.05
0.05
0.05
—
—
—
Min
—
—
—
4.95
9.95
14.95
Max
0.05
0.05
0.05
—
—
—
Min
—
—
—
4.95
9.95
14.95
Max
0.05
0.05
0.05
—
—
—
5.0
—
—
VOH
5.0
4.95
9.95
Vdc
Input Voltage** — Enable
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“0” Level
VIL
5.0
10
15
—
—
—
0.8
1.6
2.4
—
—
—
1.1
2.2
3.4
0.8
1.6
2.4
—
—
—
0.8
1.6
2.4
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Input Voltage
Other Inputs
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(Full — Sink Only)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
VIH
5.0
10
15
2.0
6.0
10
—
—
—
2.0
6.0
10
1.9
3.1
4.3
—
—
—
2.0
6.0
10
—
—
—
Vdc
“0” Level
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Source
IOH
5.0
10
1 5
– 1.0
—
—
–
—
—
– 1.0
—
—
– 2.0
– 6.0
– 12
—
—
—
– 1.0
—
—
—
—
—
mAdc
Sink
IOL
5.0
10
15
15
1.6
—
—
—
—
—
—
1.6
—
—
—
3.2
6.0
12
—
—
—
1.6
—
—
—
—
—
—
mAdc
Iin
ITL
Cin
IDD
±
0.1
±
0.1
—
±
0.00001
±
0.00001
5.0
±
0.1
±
0.1
7.5
±
1.0
±
3.0
—
μ
Adc
μ
Adc
pF
μ
Adc
Three–State Leakage Current
15
—
—
—
Input Capacitance (Vin = 0)
Quiescent Current
(Per Package)
—
—
—
—
5.0
10
15
5.0
10
—
—
—
5.0
10
20
—
—
—
IT = (2.0
μ
A/kHz) f + IDD
IT = (4.0
μ
A/kHz) f + IDD
IT = (6.0
μ
A/kHz) f + IDD
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
**Total Supply Current at an
**
External Load Capacitance of
**
130 pF
IT
μ
Adc
Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
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