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參數(shù)資料
| 型號： | MC14556BF |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Binary to 1-of-4 Decoder/Demultiplexer |
| 中文描述： | 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封裝： | EIAJ, SOP-16 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 142K |
| 代理商： | MC14556BF |
MC14555B, MC14556B
http://onsemi.com
4
(7.)
(8.)
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time — A, B to Output
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 135 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 62 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 45 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
220
95
70
440
190
140
ns
Propagation Delay Time — E to Output
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 115 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 52 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 40 ns
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
t
PLH
,
t
PHL
5.0
10
15
—
—
—
200
85
65
400
170
130
ns
Figure 1. Dynamic Power Dissipation Signal Waveforms
Figure 2. Dynamic Signal Waveforms
All 8 outputs connect to respective C
L
loads.
f in respect to a system clock.
INPUT E LOW
20 ns
20 ns
90%
50%
10%
2f
1
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
A INPUTS
(50% DUTY CYCLE)
B INPUTS
(50% DUTY CYCLE)
OUTPUT Q1
20 ns
20 ns
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
t
THL
90%
50%
10%
90%
50%
10%
90%
50%
10%
t
PLH
t
TLH
t
PHL
t
PHL
t
THL
t
PLH
t
TLH
INPUT A HIGH, INPUT E LOW
INPUT B
OUTPUT Q3
MC14556B
OUTPUT Q3
MC14555B
LOGIC DIAGRAM
(1/2 of Dual)
* Eliminated for MC14555B
*
*
*
*
Q0
Q1
Q2
Q3
E
B
A
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