
MOTOROLA CMOS LOGIC DATA
5
MC14541B
TYPICAL RC OSCILLATOR CHARACTERISTICS
Figure 4. RC Oscillator Stability
Figure 5. RC Oscillator Frequency as a
Function of Rtc and Ctc
8.0
4.0
0
–4.0
–8.0
–12
–16
125
100
75
50
25
0
–25
–55
TA, AMBIENT TEMPERATURE (
°
C)
F
VDD = 15 V
10 V
5.0 V
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25
°
C
RS = 120 k
, f = 7.8 kHz @ VDD = 10 V, TA = 25
°
C
RTC = 56 k
,
C = 1000 pF
100
50
0.1
0.2
0.5
1.0
2.0
5.0
10
20
1.0 k
10 k
RTC, RESISTANCE (OHMS)
0.001
C, CAPACITANCE (
μ
F)
100 k
1.0 m
f
0.0001
0.01
0.1
VDD = 10 V
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS
≈
2RTC)
f AS A FUNCTION
OF C
(RTC = 56 k
)
(RS = 120 k
)
OPERATING CHARACTERISTICS
With Auto Reset pin set to a “0” the counter circuit is initial-
ized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to a
“1”. Both types of reset will result in synchronously resetting
all counter stages independent of counter state. Auto Reset
pin when set to a “1” provides a low power operation.
The RC oscillator as shown in Figure 3 will oscillate with a
frequency determined by the external RC network i.e.,
1
f =
if (1 kHz
f
100 kHz)
2.3 RtcCtc
RS
≈
2 Rtc
The time select inputs (A and B) provide a two–bit address
to output any one of four counter stages (28, 210, 213 and
216). The 2n counts as shown in the Frequency Selection
Table represents the Q output of the Nth stage of the counter.
When A is “1”, 216 is selected for both states of B. However,
and
where RS
≥
10 k
when B is “0”, normal counting is interrupted and the 9th
counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”, corre-
spondingly when Q/Q select pin is set to a “1” the Q output is
a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with mode
pin “0” and after a reset condition the RS flip–flop (see Ex-
panded Block Diagram) resets, counting commences, and
after 2n–1 counts the RS flip–flop sets which causes the out-
put to change state. Hence, after another 2n–1 counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.
DIGITAL TIMER APPLICATION
Rtc
Ctc
NC
RS
AR
MR
INPUT
tMR
VDD
B
A
N.C.
OUTPUT
VDD
MODE
Q/Q
t + tMR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
When Master Reset (MR) receives a positive pulse, the in-
ternal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and re-
mains low until another input pulse is received.
This “one shot” is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy is
needed.
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up, dur-
ing which time Q output will be high.