參數(shù)資料
型號: MC145406P
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Ultra Low-Supply Current/Supply-Voltage Supervisory Circuits 6-SOT-23 -40 to 85
中文描述: LINE TRANSCEIVER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 4/12頁
文件大?。?/td> 155K
代理商: MC145406P
MC145406
4
MOTOROLA
Vin =
±
2 V
3
5
7
14
12
10
8
9
1
VDD
16
VCC
DI1
DI2
DI3
VSS
GND
Tx3
Tx2
Tx1
Rout =
Vin
I
Figure 1. Power–Off Source Resistance (Drivers)
Figure 2. Switching Characteristics
Figure 3. Slew–Rate Characterization
DRIVERS
DI1–DI3
3 V
0 V
VOH
VOL
Tx1–Tx3
tPLH
tPHL
50%
tf
tr
10%
90%
RECEIVERS
Rx1–Rx3
DO1–DO3
+ 3 V
0 V
VOH
VOL
tPLH
tPHL
tf
tr
50%
DRIVERS
Tx1–Tx3
90%
50%
10%
3 V
– 3 V
3 V
– 3 V
tSHL
tSLH
SLEW RATE (SR) =– 3 V – (3 V)OR3 V – ( – 3 V)
tSLH
tSHL
PIN DESCRIPTIONS
VDD
Positive Power Supply (Pin 1)
The most positive power supply pin, which is typically + 5
to +
12V.
VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, which is typically – 5
to –
12 V.
VCC
Digital Power Supply (Pin 16)
The digital supply pin, which is connected to the logic
power supply (maximum +
5.5 V). VCC
must
be less than
or equal to VDD.
GND
Ground (Pin 9)
Ground return pin is typically connected to the signal
ground pin of the EIA 232–E connector (Pin 7) as well as to
the logic power supply ground.
Rx1, Rx2, Rx3
Receive Data Input (Pins 2, 4, 6)
These are the EIA 232–E receive signal inputs whose
voltages can range from (VDD + 15 V) to (VSS – 15 V). A volt-
age between +
3 and (VDD + 15 V) is decoded as a space
and causes the corresponding DO pin to swing to ground (0
V); a voltage between – 3 and (VDD – 15 V) is decoded as a
mark and causes the DO pin to swing up to VCC. The actual
turn–on input switchpoint is typically biased at 1.8 V above
ground, and includes 800mV of hysteresis for noise rejec-
tion. The nominal input impedance is 5 k
. An open or
grounded input pin is interpreted as a mark, forcing the DO
pin to VCC.
DO1, DO2, DO3
Data Output (Pins 11, 13, 15)
These are the receiver digital output pins, which swing
from VCC to GND. A space on the Rx pin causes DO to pro-
duce a logic 0; a mark produces a logic 1. Each output pin is
capable of driving one LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
These are the high–impedance digital input pins to the
drivers. TTL compatibility is accomplished by biasing the in-
put switchpoint at 1.4 V above GND. However, 5–V CMOS
compatibility is maintained as well. Input voltage levels on
these pins must be between VCC and GND.
Tx1, Tx2, Tx3
Transmit Data Output(Pins 3, 5, 7)
These are the EIA 232–E transmit signal output pins,
which swing toward VDD and VSS. A logic 1 at a DI input
causes the corresponding Tx output to swing toward VSS. A
logic 0 causes the output to swing toward VDD (the output
voltages will be slightly less than VDD or VSS depending upon
the output load). Output slew rates are limited to a maximum
of 30 V per
μ
s. When the MC145406 is off (VDD = VSS = VCC
= GND), the minimum output impedance is 300
.
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