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參數(shù)資料
| 型號(hào)： | MC14516BDR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Binary Up/Down Counter |
| 中文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 221K |
| 代理商： | MC14516BDR2 |
MC14516B
http://onsemi.com
8
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while C
in
is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), C
out
goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
L.S.D.
MC14516B
C
out
Q0
PE
Q1
Q2
Q3
P0
P1
P2
P3
R
U/D
CLOCK
C
in
M.S.D.
MC14516B
C
out
Q0
PE
Q1
Q2
Q3
P0
P1
P2
P3
R
U/D
CLOCK
C
in
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
TERMINAL COUNT
INDICATOR
P0
P1
P2
P3
P4
P5
P6
P7
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
+V
DD
+V
DD
+V
DD
OPEN = COUNT
CLOCK
RESET
RESISTORS = 10 k
0 = COUNT
1 = PRESET
1 = UP
0 = DOWN
PRESET
ENABLE
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