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參數(shù)資料
| 型號(hào)： | MC141627FT |
| 廠商： | MOTOROLA INC |
| 元件分類： | 信號(hào)分離 |
| 英文描述： | Military Digital Signal Processor 172-CFP |
| 中文描述： | Y/C SEPARATOR IC, PQFP48 |
| 封裝： | QFP-48 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 236K |
| 代理商： | MC141627FT |
MC141627
7
MOTOROLA
DEVICE DESCRIPTION
INTRODUCTION
The Advanced PAL Comb Filter–II is a video signal pro-
cessor for VCRs, LDPs, and TVs. It separates the Lumi-
nance Y and Chrominance C signal from the NTSC/PAL
composite signal by using digital signal processing tech-
niques which minimize dot–crawl and cross–color. The built–
in 4xFSC PLL circuit allows a subcarrier signal input, which
generates a 4xFSC clock for video signal processing. This
filter allows a video signal input of an extended frequency
bandwidth by using a 4xFSC clock. The built–in vertical en-
hancer circuit reduces noise and dot crawl on the Luminance
Y signal. The built–in A/D and D/A converters allow easy
connection to analog video circuits.
DESCRIPTION
The simplified block diagram of the Advanced Comb
Filter–II chip is shown at the beginning of this data sheet.
There are five major functions represented in this block dia-
gram. The first block is the A/D conversion block. The high
speed 8–bit binary analog–to–digital converter converts the
incoming analog video signal to an 8–bit binary data stream.
The conversion frequency is 14.3 MHz/17.7 MHz for NTSC/
PAL, which is four times the color subcarrier frequency.
The second block contains the Advanced Comb Filter–II
algorithm. The digital data from the A/D converter is pro-
cessed by the algorithm of the Advanced Comb Filter–II. The
composite video is filtered by the band–pass filter (BPF) and
separated into the Luminance Y and Chrominance C signals.
The third block is the vertical enhancer circuit block. By
comparing pixel information from the vertical dot processing
block, the vertical enhancer emphasizes the vertical picture
outline.
The fourth block is the digital–to–analog conversion block.
Two 8–bit D/A converters convert the luminance and chromi-
nance into analog outputs. The conversion frequency is four
times the subcarrier signal (14.3 MHz/17.7 MHz). The chro-
minance analog output is biased with a dc offset of half the
value of the D/A converter reference.
The fifth block is a 4xFSC PLL CLK generation circuit. This
block generates a clock signal that is four times the subcarr-
ier signal. This signal is locked to the signal input on the FSC
pin. This signal may be selected to equal FSC or 4xFSC.
A/D Converter
The composite video signal input is converted to the digital
code by the high speed 8–bit A/D converter. The A/D con-
verter reference has a self–bias function which generates
VTP = 2.5 V, VBT = 0.5 V. This allows the A/D converter to
function without an external reference circuit.
Clamp Voltage Regulating Circuit
The input video signal may be either dc or ac coupled. By
connecting Vin to CLout, the internal clamp circuit will provide
dc restoration. The clamp voltage regulating circuit sync tip
clamps the input video signal and compares it to the digital
value of the clamp level ($04) with the A/D converter output
code. The clamp voltage, CLout, sets the dc input level when
Vin and CLout are interconnected.
Advanced Comb Filter–II
The Advanced PAL Comb Filter–II is a digital comb filter
developed for use in the NTSC/PAL system. The vertical cor-
relation circuit provides high picture quality and high resolu-
tion and requires no adjustment for its Y/C separation. The
clock frequency is 14.3 MHz, which is four times the NTSC
subcarrier.
The BYPASS pin can be used to select between the com-
posite signal output without Y/C separation and the Y/C sig-
nal output. Table 1 shows the relationship of the BYPASS pin
and each output.
Table 1. BYPASS Function
BYPASS Pin
Yout
Cout
L
Luminance
Chrominance
H
Composite
Composite
Adaptive Vertical Enhancer Circuit
The vertical enhancer circuit is an adaptive enhanced pro-
cessing using two line memories. The adaptive LPF of the
vertical enhancer circuit minimizes noise and dot–crawl. This
block does not emphasize horizontal and vertical sync sig-
nals. Table 2 shows the relationship of the VH pin and the
vertical enhancer function. The coring characteristics of the
vertical enhancer circuit can be set up using the digital port in
normal mode.
Table 2. VH Function
VH Pin
Vertical Enhancer
L
On
H
Off
D/A Converter
The luminance and chrominance signals separated in the
Advanced Comb Filter–II portion are converted to analog sig-
nals by two 8–bit D/A converters. The output voltage range is
from 0.3 V to 1.5 V, 1.2 V p–p. The sampling clock of the D/A
converter is 14.3 MHz/17.7 MHz.
Clock Generation Circuit
The block is a 4xFSC CLK generation circuit. It generates
four times the subcarrier signal which locks the inputting
subcarrier on the FSC pin at the normal (FSC) mode. At the
other mode, the external 4xFSC clock should be input.
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