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參數(shù)資料
| 型號(hào)： | MC14082BDR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | B-SUFFIX SERIES CMOS GATES |
| 中文描述： | 4000/14000/40000 SERIES, DUAL 4-INPUT AND GATE, PDSO14 |
| 封裝： | LEAD FREE, SOIC-14 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大小： | 327K |
| 代理商： | MC14082BDR2G |
MOTOROLA CMOS LOGIC DATA
11
MC14001B
SWITCHING CHARACTERISTICS*
tTLH = (0.60 ns/pF) CL + 20 ns
VDD
Output Fall Time, All B–Series Gates
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL
10
15
—
—
50
40
100
80
ns
Propagation Delay Time
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns
All Other 2, 3, and 4 Input Gates
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
tPLH, tPHL
15
—
40
80
ns
5.0
10
15
10
—
—
—
—
125
50
50
80
250
100
100
150
VDD
14
CL
VSS
7
PULSE
GENERATOR
INPUT
OUTPUT
90%
50%
10%
10%
50%
20 ns
20 ns
tPHL
tPLH
tTLH
tPHL
tTHL
tPLH
VOL
VOH
0 V
VDD
INPUT
OUTPUT
INVERTING
* All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to VSS.
90%
50%
10%
VOL
VOH
OUTPUT
NON–INVERTING
tTHL
tTLH
*
Figure 1. Switching Time Test Circuit and Waveforms
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