參數(shù)資料
型號: MC10EP446FA
廠商: ON Semiconductor
文件頁數(shù): 4/20頁
文件大?。?/td> 0K
描述: IC CONV 8BIT SER/PAR ECL 32LQFP
產(chǎn)品變化通告: Product Discontinuation 20/Aug/2008
標(biāo)準(zhǔn)包裝: 250
接口: 差分
電源電壓: 3 V ~ 5.5 V
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-LQFP(7x7)
包裝: 管件
安裝類型: 表面貼裝
其它名稱: MC10EP446FAOS
MC10EP446, MC100EP446
http://onsemi.com
12
APPLICATION INFORMATION
The MC10/100EP446 is an integrated 8:1 parallel to serial
converter. An attribute for EP446 is that the parallel inputs
D0–D7 (Pins 17 – 24) can be configured to accept either
CMOS, ECL, or TTL level signals by a combination of
interconnects between VEF (Pin 27) and VCF (Pin 26) pins.
For CMOS input levels, leave VEF and VCF open. For ECL
operation, short VCF and VEF (Pins 26 and 27). For TTL
operation, connect a 1.5 V supply reference to VCF and leave
the VEF pin open. The 1.5 V reference voltage to VCF pin can
be accomplished by placing a 1.5 k
W or 500 W between VCF
and VEE for 3.3 V or 5.0 V power supplies, respectively.
Note: all pins requiring ECL voltage inputs must have a
50
W terminating resistor to VTT (VTT = VCC – 2.0 V).
The CKSEL input (Pin 2) is provided to enable the user to
select the serial data rate output between internal clock data
rate or twice the internal clock data rate. For CKSEL LOW
operation, the time from when the parallel data is latched
to when the data is seen on the SOUT is on the falling edge
of the 7th clock cycle plus internal propagation delay
(Figure 7). Note the PCLK switches on the falling edge of
CLK.
Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW
CLK
SOUT
PCLK
D0
D02
D1
D2
D3
D4
D5
D6
D7
D22
D32
D42
D52
D62
D72
D03
D13
D23
D33
D43
D53
D63
D73
D12
CKSEL
D0
1
D1
1
D2
1
D3
1
D4
1
D5
1
D6
1
D7
1
D0
2
D1
2
D2
2
D3
2
D6
2
D01
D21
D31
D41
D51
D61
D71
D11
D5
2
D04
D14
D24
D34
D44
D54
D64
D74
123
4
567
Number of Clock Cycles from Data Latch to SOUT
Data Latched
D4
2
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