參數(shù)資料
型號: MC10EP131FA
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
中文描述: 10E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32
封裝: LQFP-32
文件頁數(shù): 1/10頁
文件大?。?/td> 90K
代理商: MC10EP131FA
Semiconductor Components Industries, LLC, 2004
January, 2004 Rev. 7
1
Publication Order Number:
MC10EP131/D
MC10EP131, MC100EP131
3.3V / 5VECL Quad D
FlipFlop with Set, Reset,
and Differential Clock
The MC10/100EP131 is a Quad Masterslaved D flipflop with
common set and separate resets. The device is an expansion of the
E131 with differential common clock and individual clock enables.
With AC performance faster than the E131 device, the EP131 is ideal
for applications requiring the fastest AC performance available.
Each flipflop may be clocked separately by holding Common
Clock (C
C
) LOW and C
C
HIGH, then using the differential Clock
Enable inputs for clocking (C
03
, C
03
).
Common clocking is achieved by holding the differential inputs
C
03
LOW and C
03
HIGH while using the differential Common
Clock (C
C
) to clock all four flipflops. When left floating open, any
differential input will disable operation due to input pulldown resistors
forcing an output default state.
Individual asynchronous resets (R
03
) and an asynchronous set
(SET) are provided.
Data enters the master when both C
C
and C
03
are LOW, and
transfers to the slave when either C
C
or C
03
(or both) go HIGH.
The 100 Series contains temperature compensation.
460 ps Typical Propagation Delay
Maximum Frequency
>
3 GHz Typical
Differential Individual and Common Clocks
Individual Asynchronous Resets
Asynchronous Set
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
EE
32
1
MCXXX
EP131
AWLYYWW
LQFP32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
XXX = 10 or 100
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
*For additional information, see Application Note
AND8002/D
Device
Package
Shipping
ORDERING INFORMATION
MC10EP131FA
LQFP32
250 Units/Tray
MC10EP131FAR2
LQFP32
2000 Tape & Reel
MC100EP131FA
LQFP32
250 Units/Tray
MC100EP131FAR2
LQFP32
2000 Tape & Reel
http://onsemi.com
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
相關(guān)PDF資料
PDF描述
MC10EP131FAR2 3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
MC10EP131 3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
MC10EP139DTR2 3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip
MC10EP139DW 3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip
MC100EP139DW 3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip
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