Table 8. AC CHARACTERISTICS VCCx
參數(shù)資料
型號: MC10E446FNR2G
廠商: ON Semiconductor
文件頁數(shù): 10/12頁
文件大小: 0K
描述: IC CONV 4BIT SER/PAR ECL 28-PLCC
產(chǎn)品變化通告: Dimensional change 21/Oct/2008
標(biāo)準(zhǔn)包裝: 500
系列: 10E
類型: 串行至并行/并行至串行轉(zhuǎn)換器
電源電壓: 4.2 V ~ 5.7 V
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
MC10E446, MC100E446
http://onsemi.com
7
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = 5.0 V (Note 9)
Symbol
Characteristic
0°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
FMAX
Max Conversion Frequency
1.3
1.6
1.3
1.6
1.3
1.6
Gb/s
NRZ
tPLH
tPHL
Propagation Delay to Output
CLK to SOUT (Note 10)
CLK to CL/4
CLK to CL/8
SYNC to CL/4, CL/8
1020
650
800
650
1200
850
1050
850
1480
1050
1300
1100
1020
650
800
650
1200
850
1050
850
1480
1050
1300
1100
1020
650
800
650
1200
850
1050
850
1480
1050
1300
1100
ps
ts
Setup Time (Note 11)
SIN, Dn
-200
-450
-200
450
200 450
ps
th
Hold Time (Note 11)
SIN, Dn
900
650
900
650
900
650
ps
tRR
Reset Recovery Time
SYNC
500
300
500
300
500
300
ps
tPW
Min Pulse Width
CLK, MR
300
ps
tJITTER
Random Clock Jitter (RMS)
< 1
ps
VPP
Input Voltage Swing (Differential Configuration)
150
1000
150
1000
150
1000
mV
tr
tf
Rise/Fall Times (20% - 80%)
SOUT
Other
100
200
225
425
350
650
100
200
225
425
350
650
100
200
225
425
350
650
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary 0.46 V / +0.06 V.
100 Series: VEE can vary 0.46 V / +0.8 V.
10.Propagation delays measured from negative going clock edge.
11. Relative to negative clock edge.
CLK
D
th
ts
Valid Data
Setup
Hold
CLK
SYNC
trr
Figure 3.
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