參數(shù)資料
型號(hào): MC100EP451FAR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 3.3V / 5VECL 6-Bit Differential Register with Master Reset
中文描述: 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32
封裝: LQFP-32
文件頁(yè)數(shù): 3/8頁(yè)
文件大?。?/td> 226K
代理商: MC100EP451FAR2
Advanced Clock Drivers Devices
Freescale Semiconductor
3
MC100ES6210
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VTT
Output Termination Voltage
VCC – 2(1)
1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase.
V
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
CDM
ESD Protection (Charged Device Model)
V
LU
Latch-Up Immunity
200
mA
CIN
Input Capacitance
4.0
pF
Inputs
θJA
Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
JESD 51-6, 2S2P multilayer test board
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
θJC
Thermal Resistance Junction to Case
23.0
26.3
°C/W
MIL-SPEC 883E
Method 1012.1
TJ
Operating Junction Temperature(2)
(continuous operation)
MTBF = 9.1 years
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110
°C junction temperature allowing the MC100ES6210 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6210 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
110
°C
Table 4. PECL DC Characteristics (VCC = 2.5 V ± 5% or VCC = 3.3 V ± 5%, VEE = GND, TJ = 0°C to +110°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals)
VPP
Differential Input Voltage(1)
1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
0.1
1.3
V
Differential operation
VCMR
Differential Cross Point Voltage(2)
2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
1.0
VCC – 0.3
V
Differential operation
IIN
Input Current(1)
±100
AVIN = VIL or VIN = VIH
PECL Clock Outputs (QA0-4, QA0-4, QB0-4, QB0-4)
VOH
Output High Voltage
VCC –1.2
VCC –1.005
VCC –0.7
V
IOH = –30 mA(3)
3. Equivalent to a termination of 50
to VTT.
VOL
Output Low Voltage
VCC = 3.3 V±5%
VCC = 2.5 V±5%
VCC –1.9
VCC –1.705
VCC –1.5
VCC –1.3
VIOL = –5 mA(3)
Supply Current and VBB
IEE
Maximum Quiescent Supply Current
without Output Termination Current
60
100
mA
VEE pin
VBB
Output Reference Voltage
VCC –1.38
VCC –1.26
VCC –1.14
V
IBB = 0.2 mA
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