參數資料
型號: MC100EP196
廠商: ON SEMICONDUCTOR
英文描述: 3.3V ECL Programmable Delay Chip with FTUNE
中文描述: 3.3 ECL可編程延時芯片與FTUNE
文件頁數: 6/8頁
文件大?。?/td> 226K
代理商: MC100EP196
Advanced Clock Drivers Devices
6
Freescale Semiconductor
MC100ES6210
PACKAGE DIMENSIONS
12 REF
DIM
MIN
MAX
MILLIMETERS
A
A1
7.00 BSC
A2
0.80 BSC
b
9.00 BSC
b1
0.30
0.40
c
0.09
0.20
c1
0.09
0.16
D
D1
e
E
E1
L
L1
1.00 REF
R1
0.08
0.20
R2
S
1
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.08
---
0
7
9.00 BSC
7.00 BSC
0.50
0.70
q
0.20 REF
D1
D/2
E
E1
1
8
9
17
25
32
D1/2
E1/2
E/2
4X
D
7
A
D
B
A-B
0.20 H
D
4X
A-B
0.20 C
D
6
4
DETAIL G
PIN 1 INDEX
DETAIL AD
R R2
θ
(S)
L
(L1)
0.25
GAUGE PLANE
A2
A
A1
(
θ1)
8X
R R1
e
SEATING
PLANE
DETAIL AD
0.1 C
C
32X
28X
H
DETAIL G
F
e/2
A, B, D
3
SECTION F-F
BASE
c1
c
b
b1
METAL
A-B
M
0.20
D
C
5
8
PLATING
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
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