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參數(shù)資料
| 型號(hào)： | MC100EP195BMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 100EP |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.5ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.2ns ~ 12.2ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC100EP195BMNR4GOSCT |
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Semiconductor Components Industries, LLC, 2008
September, 2008 Rev. 1
1
Publication Order Number:
MC100EP195B/D
MC100EP195B
3.3V ECL Programmable
Delay Chip
Descriptions
The MC100EP195B is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay
increment of the EP195B has a digitally selectable resolution of about
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level
signals. Because the EP195B is designed using a chain of multiplexers
it has a fixed minimum delay of 2.2 ns. An additional pin D10 is
provided for controlling Pins 14 and 15, CASCADE and CASCADE,
also latched by LEN, in cascading multiple PDCs for increased
programmable range. The cascade logic allows full control of multiple
PDCs. Switching devices from all “1” states on D[0:9] with SETMAX
LOW to all “0” states on D[0:9] with SETMAX HIGH will increase
the delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave VCF and VEF open. For ECL operation, short VCF and
VEF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
supply reference to VCF and leave open VEF pin. The 1.5 V reference
voltage to VCF pin can be accomplished by placing a 2.2 kW resistor
between VCF and VEE for a 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For singleended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range:
VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 3.0 V to 3.6 V
IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels
A Logic High on the EN Pin Will Force Q to Logic Low
D[10:0] Can Select Either LVPECL, LVCMOS, or
LVTTL Input Levels
VBB Output Reference Voltage
These are PbFree Devices
MARKING
DIAGRAMS*
A
= Assembly Location
WL, L
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
ORDERING INFORMATION
QFN32
MN SUFFIX
CASE 488AM
32
1
MC100
EP195B
ALYWG
1
32
1
LQFP32
FA SUFFIX
CASE 873A
MC100
EP195B
AWLYYWWG
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP195FA | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAG | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAG | 制造商:ON Semiconductor 功能描述:DELAY LINE IC |
| MC100EP195FAR2 | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195FAR2G | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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