參數(shù)資料
型號(hào): MC100EP016FA
廠商: ON SEMICONDUCTOR
元件分類(lèi): 通用總線功能
英文描述: GT 7C 7#12 PIN RECP LINE
中文描述: 100EP SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQFP32
封裝: LQFP-32
文件頁(yè)數(shù): 4/8頁(yè)
文件大小: 226K
代理商: MC100EP016FA
Advanced Clock Drivers Devices
4
Freescale Semiconductor
MC100ES6210
Table 5. ECL DC Characteristics (VEE = 2.5 V ± 5% or VEE = 3.3 V ± 5%, VCC = GND, TJ = 0°C to +110°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals)
VPP
Differential Input Voltage(1)
1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
0.1
1.3
V
Differential operation
VCMR
Differential Cross Point Voltage(2)
2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
VEE + 1.0
–0.3
V
Differential operation
IIN
Input Current(1)
±100
AVIN = VIL or VIN = VIH
ECL Clock Outputs (QA0–4, QA0–4, QB0–4, QB0–4)
VOH
Output High Voltage
–1.2
–1.005
–0.7
V
IOH = –30 mA(3)
3. Equivalent to a termination of 50
to VTT.
VOL
Output Low Voltage
VCC = 3.3 V ±5%
VCC = 2.5 V ±5%
–1.9
–1.705
–1.5
–1.3
VIOL = –5 mA(3)
Supply Current and VBB
IEE
Maximum Quiescent Supply Current
without Output Termination Current
60
100
mA
VEE pin
VBB
Output Reference Voltage
–1.38
–1.26
–1.14
V
IBB = 0.2 mA
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