參數(shù)資料
型號： MB9BF518TPMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176
文件頁數(shù)： 70/124頁
文件大?。?/td> 1191K
代理商： MB9BF518TPMC
5
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r1.0
MB9B510T Series
DS706-00019-0v01-E
Watch Counter
The Watch counter is used for wake up from power saving mode.
·
Interval timer: up to 64s(Max)@ Sub Clock : 32.768kHz
External Interrupt Controller Unit
·
Up to 32 external interrupt input pin
·
Include one non-maskable interrupt(NMI)
Watch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low speed internal CR oscillator. Therefore, "Hardware"
watchdog is active in any power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
·
CCITT CRC16 Generator Polynomial: 0x1021
·
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
·
Main Clock
: 4MHz to 48MHz
·
Sub Clock
: 32.768kHz
·
High-speed internal CR Clock
: 4MHz
·
Low-speed internal CR Clock
: 100kHz
·
Main PLL Clock
[Resets]
·
Reset requests from INITX pin
·
Power on reset
·
Software reset
·
Watchdog timers reset
·
Low voltage detector reset
·
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
·
External OSC clock failure (clock stop) is detected, reset is asserted.
·
External OSC frequency anomaly is detected, interrupt or reset is asserted.
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