參數(shù)資料
型號(hào)： MB95F118BSPV2
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PBCC48
封裝： 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LCC-48
文件頁數(shù)： 32/68頁
文件大?。?/td> 2637K
代理商： MB95F118BSPV2
MB95110B Series
38
DS07-12615-3E
(2) Source Clock/Machine Clock
(Vcc
= 3.3 V, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes
the machine clock. Further, the source clock can be selected as follow.
Main clock divided by 2
PLL multiplication of main clock (select from 1, 2, 2.5 4 multiplication)
Sub clock divided by 2
PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follow.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter
Sym-
bol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Source clock*1
(Clock before setting
division)
tSCLK
61.5
2000
ns
When using Main clock
Min : FCH
= 8.125 MHz, PLL multiplied by 2
Max : FCH
= 1 MHz, divided by 2
7.6
61.0
μs
When using Sub clock
Min : FCL
= 32 kHz, PLL multiplied by 4
Max : FCL
= 32 kHz, divided by 2
Source clock frequency
FSP
0.5
16.25
MHz When using Main clock
FSPL
16.38
4
131.072 kHz When using Sub clock
Machine clock*2
(Minimum instruction
execution time)
tMCLK
100
32000
ns
When using Main clock
Min : FSP
= 16.25 MHz, no division
Max : FSP
= 0.5 MHz, divided by 16
7.6
976.5
μs
When using Sub clock
Min : FSPL
= 131 kHz, no division
Max : FSPL
= 16 kHz, divided by 16
Machine clock
frequency
FMP
0.031
16.250
MHz When using Main clock
FMPL
1.024
131.072 kHz When using Sub clock
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