參數(shù)資料
型號: MB91F475PMC1-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 93/94頁
文件大?。?/td> 0K
描述: IC MCU 256KB FLASH 144-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: FR MB91470
核心處理器: FR60 RISC
芯體尺寸: 32-位
速度: 80MHz
連通性: EBI/EMI,I²C,F(xiàn)IFO,SIO
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 113
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8/10b,4x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
其它名稱: 865-1093
95
32015G–AVR32–09/09
AT32AP7001
Figure 11-2. PLL with control logic and filters
11.5.3.1
Enabling the PLL
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLDIV and PLLMUL bitfields must be written with the division and multipli-
cation factor, respectively, creating the PLL frequency:
f
PLL = (PLLMUL+1) / (PLLDIV+1) fOSC
The LOCKn flag in ISR is set when PLLn becomes locked. The bit will stay high until cleared by
writing 1 to ICR:LOCKn. The Power Manager interrupt can be triggered by writing IER:LOCKn to
1.
Note that the input frequency for the PLL must be within the range inidicated in the Electrical
Characteristics chapter. The input frequency for the PLL relates to the oscillator frequency and
PLLDIV setting as follows:
f
PLLIN = 2 fOSC / (PLLDIV+1)
PLL
Output
Divider
Input
Divider
LFT
0
1
Osc0 clock
Osc1 clock
PLLOSC
PLLEN
PLLOPT
PLLMUL
PLLDIV
Lock
Suppression
PLLCOUNT
LOCK
Mask
PLL clock
C1
R1
C2
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