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| 型號(hào)： | MB91F313APMC-GE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LFQFP-120 |
| 文件頁(yè)數(shù)： | 47/72頁(yè) |
| 文件大?。?/td> | 1975K |
| 代理商： | MB91F313APMC-GE1 |
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MB91313/A Series
DS07-16706-3E
51
4.
AC Characteristics
(1) Clock Timing
(VDDE
= 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = 40 °C to + 85 °C)
(2) Clock Output Timing
(VDDE
= AVCC = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = AVSS = 0 V, Ta = 40 °C to + 85 °C)
*1 : tCYC is the frequency of one clock cycle after gearing.
*2 : These ratings are for the gear ratio set to
× 1.
For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the
following equation.
(1/2
× 1/n) × tCYC 10
*3 : These ratings are for the gear ratio set to
× 1.
(3) PLL Oscillation Stabilization Wait Time
(VDDE
= 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = 40 °C to + 85 °C)
Parameter
Symbol
Pin
name
Condi-
tions
Value
Unit
Remarks
Min
Typ
Max
Clock frequency
fC
X0, X1
10
16.5
33
MHz
PLL clock (self-oscillation
16.5 MHz doubled via
PLL : internal operation at
33 MHz Max.)
Sub clock frequency
fclk
X0A,
X1A
32.768
kHz
Internal operating
clock frequency
fCP
33
MHz CPU
fCPP
33
MHz Peripheral
fCPT
16.5
MHz External bus
Parameter
Symbol
Pin
name
Conditions
Value
Unit
Remarks
Min
Max
Cycle time
tCYC
CLK
60.7
ns
*1
CLK
↑ → CLK ↓
tCHCL
CLK
1/2
× tCYC 51/2 × tCYC + 5ns *2
CLK
↓ → CLK ↑
tCLCH
CLK
1/2
× tCYC 51/2 × tCYC + 5ns *3
Parameter
Symbol
Value
Unit
Remarks
Min
Max
PLL oscillation stabilization
wait time
tLOCK
600
s
The length of time to wait for the PLL
oscillations to stabilize.
CLK
tCYC
VOH
VOL
VOH
tCHCL
tCLCH
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