參數(shù)資料
型號(hào)： MB91F133PBT
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-Bit RISC Microcontroller
中文描述： 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PBGA144
封裝： PLASTIC, FBGA-144
文件頁數(shù)： 110/123頁
文件大小： 1362K
代理商： MB91F133PBT
MB91133/MB91F133
110
Shift arithmetic instructions (9 instructions)
Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer
instruction) (3 instructions)
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.
If an immediate value contains relative value or external reference, assembler selects i32.
Memory load instructions (13 instructions)
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8
→
o8 = disp8:Each disp is a code extension.
disp9
→
o8 = disp9>>1:Each disp is a code extension.
disp10
→
o8 = disp10>>2:Each disp is a code extension.
udisp6
→
u4 = udisp6>>2:udisp4 is a 0 extension.
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LSL
* LSL
LSL
LSL2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
B6
B4
B4
B5
1
1
1
1
C C – C
C C – C
C C – C
C C – C
Ri<<Rj
→
Ri
Ri<<u5
→
Ri
Ri<<u4
→
Ri
Ri<<(u4 + 16)
→
Ri
Ri>>Rj
→
Ri
Ri>>u5
→
Ri
Ri>>u4
→
Ri
Ri>>(u4 + 16)
→
Ri
Ri>>Rj
→
Ri
Ri>>u5
→
Ri
Ri>>u4
→
Ri
Ri>>(u4 + 16)
→
Ri
Logical shift
LSR
* LSR
LSR
LSR2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
B2
B0
B0
B1
1
1
1
1
C C – C
C C – C
C C – C
C C – C
Logical shift
ASR
* ASR
ASR
ASR2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
BA
B8
B8
B9
1
1
1
1
C C – C
C C – C
C C – C
C C – C
Logical shift
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LDI: 32
LDI: 20
#i32, Ri
#i20, Ri
LDI: 8
* LDI
#i8, Ri
# {i8 | i20 | i32}, Ri
*
1
E
C
B
9F – 8
9B
C0
3
2
1
– – – –
– – – –
– – – –
i32
→
Ri
i20
→
Ri
i8
→
Ri
{i8 | i20 | i32}
→
Ri
Upper 12 bits are zero-
extended
Upper 24 bits are zero-
extended
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LD
LD
LD
LD
LD
LD
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp10), Ri
@(R15, udisp6), Ri
@R15 +, Ri
@R15 +, Rs
LD
@R15 +, PS
A
A
B
C
E
E
E
04
00
20
03
07 – 0
07 – 8
07 – 9
b
b
b
b
b
b
1 + a + b
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C C C C
(Rj)
→
Ri
(R13 + Rj)
→
Ri
(R14 + disp10)
→
Ri
(R15 + udisp6)
→
Ri
(R15)
→
Ri, R15 + = 4
(R15)
→
Rs, R15 + = 4
(R15)
→
PS, R15 + = 4
(Rj)
→
Ri
(R13 + Rj)
→
Ri
(R14 + disp9)
→
Ri
(Rj)
→
Ri
(R13 + Rj)
→
Ri
(R14 + disp8)
→
Ri
Rs:Special-purpose
register
LDUH
LDUH
LDUH
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp9), Ri
A
A
B
05
01
40
b
b
b
– – – –
– – – –
– – – –
Zero-extension
Zero-extension
Zero-extension
LDUB
LDUB
LDUB
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp8), Ri
A
A
B
06
02
60
b
b
b
– – – –
– – – –
– – – –
Zero-extension
Zero-extension
Zero-extension
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