參數(shù)資料
型號: MB91F133APMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 54/116頁
文件大?。?/td> 2730K
代理商: MB91F133APMC
MB91130 Series
42
DS07-16308-3E
2.
I/O Port
MB91130 series can be used as an I/O port when the setting for resources dealing with each pin does not use
the pin for input/output.
As regards the read value of the port (PDR) , the pin level is read out when input is set for the port. If output is
set, the data register value is read out. This is the same for reading under Read Modify Write.
If the input setting is changed to output setting, output data should be set first. If Read Modify Write instructions
(i.e. bit set) are used in this case, the data that is read out is the input data from the pin and is not the latch value
of the data register, so care must be taken.
Basic I/O Port Block Diagram
I/O Port Register
The I/O port consists of the Port Data Register (PDR) and Port Direction Register (DDR) .
In case of input mode (DDR
= “0”)
When PDR reads : Level of external pins handled is read out.
When PDR writes : Set value is written in PDR.
In case of output mode (DDR
= “1”)
When PDR reads : PDR values are read out.
When PDR writes : PDR values are output to the external pin handled.
Switching control for resources and ports of the analog pin (A/D)
Resources and ports of the analog pin (A/D) are switched using the Analog Input Control register on Port K
(AICK) .
This controls whether Port K is used as an analog or general-purpose port.
0 : General-purpose port
1 : Analog input (A/D)
Data bus
PDR read
Resource input
Resource output
permission
0
1
0
1
pin
PDR
DDR
PDR : Port Data Register
DDR : Data Direction Register
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