參數(shù)資料
型號(hào)： MB91340PMT
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 66 MHz, RISC MICROCONTROLLER, PQFP176
封裝： PLASTIC, LQFP-176
文件頁(yè)數(shù)： 39/126頁(yè)
文件大小： 1501K
代理商： MB91340PMT
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MB91340/MB91V340
2
Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store
instructions
Easier assembler coding: Register interlock function
Internal multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupt (PC, PS save) : 6 cycles, 16 priority levels
Harvard architecture for simultaneous program and data access
Linear access to large 4 GB memory space
Instructions compatible with FR series
2.
Bus interface
Operating frequency : Max 33MHz
Full 24-bit address output (16MB memory space)
8-bit or 16-bit data input/output (The MB91V340 supports 32-bit data input/output)
Built-in pre-fetch buffer
Unused data and address pins can be used as general-purpose input/output ports
Eight fully independent chip select outputs, can be set in minimum 64 KB units
Supports the following memory interfaces
SRAM, ROM/Flash
Page mode flash ROM, page mode ROM interface
Burst mode flash ROM (selectable burst length = 1, 2, 4, or 8)
Basic bus cycle : 2 cycles
Automatic wait cycle generation function can insert wait cycles, independently programmable for each memory
area
RDY input for external wait cycles
DMA supports fly-by transfer with independent I/O wait control
3.
Internal memory
64 KB mask ROM
4 KB data RAM
112 KB RAM. In addition to use as data RAM, this RAM area can also be used for reading and writing of
instruction codes. (128 KB on the MB91V340)
4.
Instruction cache (MB91V340 only)
Size : 4 KB
2-way set associative
4 words (16 bytes) per set
Lock function enables program code to be made cache-resident
Areas not used for instruction cache can be used as instruction RAM
5.
DMAC (DMA Controller)
5-channel (3-channel external-to-external)
3 transfer triggers : External pin, internal peripheral, software
Addressing using 32-bit full addressing mode (increment, decrement, fixed)
Transfer modes : Demand transfer, burst transfer, step transfer, or block transfer
Supports fly-by transfer (between external I/O and memory)
Selectable transfer data size : 8, 16, or 32-bit
(Continued)
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