MB91133/MB91F133
117
20-bit delayed branch macro instructions
*1: CALL20:D
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20
#label20, Ri
CALL:D @Ri
*2: BRA20:D
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20
#label20, Ri
JMP:D
@Ri
*3: Bcc20:D (BEQ20:D to BHI20:D)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20
#label20, Ri
JMP:D
@Ri
false:
Mnemonic
Operation
Remarks
* CALL20:D label20, Ri
* BRA20:D label20, Ri
* BEQ20:D label20, Ri
* BNE20:D label20, Ri
* BC20:D
* BNC20:D label20, Ri
* BN20:D
* BP20:D
* BV20:D
* BNV20:D label20, Ri
* BLT20:D
* BGE20:D label20, Ri
* BLE20:D
* BGT20:D label20, Ri
* BLS20:D
* BHI20:D
Next instruction address + 2
→
RP label20
→
PC
label20
→
PC
if (Z = = 1) then label20
→
PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
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3
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label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri