參數(shù)資料
型號(hào)： MB911110PMT2
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144
封裝： PLASTIC, LQFP-144
文件頁(yè)數(shù)： 3/112頁(yè)
文件大小： 1294K
代理商： MB911110PMT2
MB91110 Series
100
Shift arithmetic instructions (9 instructions)
Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer
instruction) (3 instructions)
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.
If an immediate value contains relative value or external reference, assembler selects i32.
Memory load instructions (13 instructions)
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8
→ o8 = disp8:Each disp is a code extension.
disp9
→ o8 = disp9>>1:Each disp is a code extension.
disp10
→ o8 = disp10>>2:Each disp is a code extension.
udisp6
→ u4 = udisp6>>2:udisp4 is a 0 extension.
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LSL
Rj, Ri
* LSL
#u5, Ri
LSL
#u4, Ri
LSL2
#u4, Ri
A
C’
C
B6
B4
B5
1
CC – C
Ri<<Rj
→ Ri
Ri<<u5
→ Ri
Ri<<u4
→ Ri
Ri<<(u4 + 16)
→ Ri
Logical shift
LSR
Rj, Ri
* LSR
#u5, Ri
LSR
#u4, Ri
LSR2
#u4, Ri
A
C’
C
B2
B0
B1
1
CC – C
Ri>>Rj
→ Ri
Ri>>u5
→ Ri
Ri>>u4
→ Ri
Ri>>(u4 + 16)
→ Ri
Logical shift
ASR
Rj, Ri
* ASR
#u5, Ri
ASR
#u4, Ri
ASR2
#u4, Ri
A
C’
C
BA
B8
B9
1
CC – C
Ri>>Rj
→ Ri
Ri>>u5
→ Ri
Ri>>u4
→ Ri
Ri>>(u4 + 16)
→ Ri
Logical shift
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LDI: 32
#i32, Ri
LDI: 20
#i20, Ri
LDI: 8
#i8, Ri
* LDI
# {i8 | i20 | i32}, Ri
*1
E
C
B
9F – 8
9B
C0
3
2
1
––––
i32
→ Ri
i20
→ Ri
i8
→ Ri
{i8 | i20 | i32}
→ Ri
Upper 12 bits are zero-
extended
Upper 24 bits are zero-
extended
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LD
@Rj, Ri
LD
@(R13, Rj), Ri
LD
@(R14, disp10), Ri
LD
@(R15, udisp6), Ri
LD
@R15 +, Ri
LD
@R15 +, Rs
LD
@R15 +, PS
A
B
C
E
04
00
20
03
07 – 0
07 – 8
07 – 9
b
1 + a + b
––––
CCCC
(Rj)
→ Ri
(R13 + Rj)
→ Ri
(R14 + disp10)
→ Ri
(R15 + udisp6)
→ Ri
(R15)
→ Ri, R15 + = 4
(R15)
→ Rs, R15 + = 4
(R15)
→ PS, R15 + = 4
Rs: Special-purpose
register
LDUH
@Rj, Ri
LDUH
@(R13, Rj), Ri
LDUH
@(R14, disp9), Ri
A
B
05
01
40
b
––––
(Rj)
→ Ri
(R13 + Rj)
→ Ri
(R14 + disp9)
→ Ri
Zero-extension
LDUB
@Rj, Ri
LDUB
@(R13, Rj), Ri
LDUB
@(R14, disp8), Ri
A
B
06
02
60
b
––––
(Rj)
→ Ri
(R13 + Rj)
→ Ri
(R14 + disp8)
→ Ri
Zero-extension
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