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參數(shù)資料
| 型號： | MB90W224AZF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CQFP120 |
| 封裝： | CERAMIC, QFP-120 |
| 文件頁數(shù)： | 44/105頁 |
| 文件大?。?/td> | 1700K |
| 代理商： | MB90W224AZF |
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43
MB90220 Series
5. 10-bit A/D Converter
The 10-bit A/D converter converts analog input voltage into a digital value. The features of this module are
described below:
Conversion time: 6.125
s/channel (min.) (with machine clock running at 16 MHz)
Uses RC-type sequential comparison and conversion method with built-in sample and hold circuit
10-bit resolution
Analog input can be selected by software from among 16 channels
Single-conversion mode:
Selects and converts one channel.
Scan conversion mode:
Converts several consecutive channels (up to 16 can be programmed).
One-shot mode:
Converts the specified channel once and terminates.
Continuous conversion mode: Repeatedly converts the specified channel.
Stop conversion mode:
Pauses after converting one channel and waits until the next startup (permits
synchronization of start of conversion).
When A/D conversion is completed, an “A/D conversion complete” interrupt request can be issued to the CPU.
Because the generation of this interrupt can be used to start up the EI2OS and transfer the A/D conversion
results to memory, this function is suitable for continuous processing.
Startup triggers can be selected from among software, an external trigger (falling edge), and a timer (rising
edge).
(1) Register Configuration
bit7
bit6
bit5
bit4
bit3
bit2
bit1
ANS3
ANS2
ANS1
ANS0
ANE3
ANE2
ANE1
ANE0
bit0
000032H
ADCH
00000000 B
bit15
bit14
bit13
bit12
bit11
bit10
bit9
—
MOD1
MOD0
STS1
STS0
bit8
(R/W)
(—)
(R/W)
(—)
(W)
(R/W)
BUSY
INT
INTE
PAUS
—
STRT
(—)
(R/W)
(W)
(R/W)
(—)
(R/W)
D7
D6
D5
D4
D3
D2
D1
D0
000033H
ADMD
- - - X0000 B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000034H
ADCS
0000 - - 00 B
XXXXXXXX B
000036H
ADCD
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Register name Address
This register specfies the A/D converter conversion channel.
This register specfies the A/D converter operation mode and the startup source.
This register is the A/D converter control and status register.
Note: Program “0” to bit 12 when write. Read value is indeterminated.
This register stores the A/D converter conversion data.
Register name Address
Initial value
(R/W)
Reserved
(R)
A/D Channel Setting Register (ADCH)
A/D Mode Register (ADMD)
A/D Control Status Register (ADCS)
A/D Data Register (ADCD)
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