![](http://datasheet.mmic.net.cn/30000/MB90W224AZF_datasheet_2367782/MB90W224AZF_25.png)
25
MB90220 Series
s I/O MAP
(Continued)
Address
Register
name
Access
Resouce
name
Initial value
000000H*3
Port 0 data register
PDR0
R/W
Port 0
X XXXXXXX
000001H*3
Port 1 data register
PDR1
R/W
Port 1
X XXXXXXX
000002H*3
Port 2 data register
PDR2
R/W
Port 2
X XXXXXXX
000003H*3
Port 3 data register
PDR3
R/W
Port 3
X XXXXXXX
000004H*3
Port 4 data register
PDR4
R/W
Port 4
X XXXXXXX
000005H*3
Port 5 data register
PDR5
R/W
Port 5
X XXXXXXX
000006H
Port 6 data register
PDR6
R/W
Port 6
1 1111111
000007H
Port 7 data register
PDR7
R
Port 7
X XXXXXXX
000008H
Port 8 data register
PDR8
R/W
Port 8
X XXXXXXX
000009H
Port 9 data register
PDR9
R/W
Port 9
1 1111111
00000AH
Port A data register
PDRA
R/W
Port A
X XXXXXXX
00000BH
Port B data register
PDRB
R/W
Port B
X XXXXXXX
00000CH
Port C data register
PDRC
R/W
Port C
– – XXXXXX
00000DH
to 0FH
(Reserved area)*1
000010H*3
Port 0 data direction register
DDR0
R/W
Port 0
0 0000000
000011H*3
Port 1 data direction register
DDR1
R/W
Port 1
0 0000000
000012H*3
Port 2 data direction register
DDR2
R/W
Port 2
0 0000000
000013H*3
Port 3 data direction register
DDR3
R/W
Port 3
0 0000000
000014H*3
Port 4 data direction register
DDR4
R/W
Port 4
0 0000000
000015H*3
Port 5 data direction register
DDR5
R/W
Port 5
0 0000000
000016H
Port 6 analog input enable register
ADER0
R/W
Port 6
1 1111111
000017H
Port 7 data direction register
DDR7
R/W
Port 7
1 1111111
000018H
Port 8 data direction register
DDR8
R/W
Port 8
0 0000000
000019H
Port 9 analog input enable register
ADER1
R/W
Port 9
1 1111111
00001AH
Port A data direction register
DDRA
R/W
Port A
0 0000000
00001BH
Port B data direction register
DDRB
R/W
Port B
0 0000000
00001CH
Port C data direction register
DDRC
R/W
Port C
–– 000000
00001DH
to 1FH
(Reserved area)*1
000020H
Mode control register 0
UMC0
R/W
UART 0 (ch.0)
0 0000100
000021H
Status register 0
USR0
R/W
0 0010000
000022H
Input data register 0
/output data register 0
UIDR0
/UODR0
R/W
X XXXXXXX