參數(shù)資料
型號： MB90M407PF
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 36/68頁
文件大小： 1486K
代理商： MB90M407PF
MB90M405 Series
DS07-13718-3E
41
Block Diagram of 8/10 Bit A/D Converter
A/D control status register 0/1 (ADCS0/ADCS1)
The A/D control status register 1 (ADCS1) has functions to set the A/D conversion start factor, enable/disable
interrupt requests, check the status of interrupt requests, and check whether A/D conversion is halted/ongoing.
A/D data register (ADCR0/ADCR1)
This register stores the results of A/D conversion. It has functions to set the A/D conversion resolution, A/D
conversion sampling time, and A/D conversion comparison time.
A/D conversion channel setting register (ADMR)
Provides a function to set the A/D conversion start/stop channel
Clock selector
This selector sets the A/D conversion start clock. The 16-bit reload timer 1 output can be set in the start clock.
Decoder
This circuit sets the analog input pin to use from the setting of the A/D conversion end channel setting bit
(ANE0 to ANE3) and A/D conversion start channel setting bit (ANS0 to ANS3) of the A/D control status register
(ADCS0) .
BUSY INT
INTE PAUS STS1 STS0 STRT
MD1 MD0
ANS2
ANS3
ANS1 ANS0
ANE2
ANE3
ANE1 ANE0
S10
ST1
ST0
CT1
CT0
D9
D7
D6
D4
D3
D2
D1
D0
AVR
AVCC
AVSS
D8
D5
φ
2
8
2
PB7/AN15
PA0/AN0
A/D control status
register
(ADCS0/ADCS1)
Interrupt request signal #37 (25H) *
16-bit reload
timer 1 output
Clock selector
Decoder
Analog
channel
selector
Sample hold
Circuit
Comparator
Control circuit
D/A converter
A/D data register
(ADCR0/ADCR1)
Inter
nal
data
b
u
s
Rese-
rved
A/D cmversion channel setting register (ADMR)
to
φ : Machine clock
* : Interrupt signal
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