參數(shù)資料
型號: MB90246A
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16位微控制器專有
文件頁數(shù): 40/100頁
文件大?。?/td> 1956K
代理商: MB90246A
40
MB90246A Series
(2) Input Capture (ICU)
The input capture (ICU) consists of a capture register corresponding to two 16-bit external input pins, a control
register, and an edge detector. Upon input of a trigger edge through an external input pin, the counter value of
the 16-bit free-run timer is stored into the input capture register, and an interrupt request can be generated
concurrently.
A capture interrupt can be generated independently for each capture unit.
The extended intelligent I/O service (EI
2
OS) can be activated.
A trigger edge direction can be selected from rising/falling/both edges.
Since two input capture units can be operated independent of each other, up to two events can be measured
independently.
The input capture function is suited for measurements of intervals (frequencies) and pulse-widths.
Register configuration
Block diagram
bit 1. . . . . . . . . . . . .
Input capture control status register (ICS)
Address
ICP0
ICP1
(Vacancy)
bit 7
bit 6
bit 5
bit 4
Initial value
00000000
B
ICE0
ICE1
EG10
EG11
EG00
EG01
bit 3
bit 2
bit 1
bit 0
Input capture register (IPCP0, IPCP1)
Address
IPCP0 : 000061
H
IPCP1 : 000063
H
IPCP0 : 000060
H
IPCP1 : 000062
H
bit 15
Initial value
XXXXXXXX
B
XXXXXXXX
B
bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICS0 : 000064
H
R/W : Readable and writable
R : Read only
X : Indeterminate
16-bit free-run timer
I
Input capture register 1 (IPCP1)
Input capture register 0 (IPCP0)
Edge detection circuit
P71/ASR1
Pin
Pin
P70/ASR0
ICP1 ICP0 ICE1 ICE0
EG11 EG10 EG01 EG00
#17 (11
H
)
#15 (OF
H
)
Input capture
control status
register(ICS)
Input capture
interrupt request
(ICU)
*: Interrupt number
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