x
3.8.5
3.8.6
3.8.7
3.9
Standby Control Register (STBC) .................................................................................................. 78
State Transition Diagram 1 (Dual Clock) ....................................................................................... 80
Notes on Using Standby Mode ...................................................................................................... 83
Memory Access Mode ........................................................................................................................ 85
CHAPTER 4
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.8
4.8.1
4.8.2
4.9
4.9.1
4.9.2
4.10 Port 8 ................................................................................................................................................ 134
4.10.1 Registers of Port 8 (PDR8, DDR8) .............................................................................................. 137
4.10.2 Operation of Port 8 ...................................................................................................................... 139
4.11 Port 9 ................................................................................................................................................ 141
4.11.1 Registers of Port 9 (PDR9, DDR9) .............................................................................................. 144
4.11.2 Operation of Port 9 ...................................................................................................................... 146
4.12 Port A ................................................................................................................................................ 148
4.12.1 Register of Port A (PDRA) ........................................................................................................... 150
4.12.2 Operation of the Port A ................................................................................................................ 151
4.13 Port B ................................................................................................................................................ 152
4.13.1 Register of Port B (PDRB) ........................................................................................................... 155
4.13.2 Operation of Port B ...................................................................................................................... 156
4.14 Program Example of the I/O Ports .................................................................................................... 157
I/O PORT ..................................................................................................... 87
Overview of the I/O Port ...................................................................................................................... 88
Port 0 .................................................................................................................................................. 91
Registers of Port 0 (PDR0, DDR0) ................................................................................................ 93
Operation of Port 0 ........................................................................................................................ 94
Port 1 .................................................................................................................................................. 96
Registers of the Port 1 (PDR1, DDR1) .......................................................................................... 98
Operation of the Port 1 ................................................................................................................ 100
Port 2 ................................................................................................................................................ 102
Registers of Port 2 (PDR2, DDR2) .............................................................................................. 104
Operation of Port 2 ...................................................................................................................... 106
Port 3 ................................................................................................................................................ 108
Register of Port 3 (PDR3) ............................................................................................................ 111
Operation of Port 3 ...................................................................................................................... 112
Port 4 ................................................................................................................................................ 113
Register of Port 4 (PDR4) ............................................................................................................ 115
Operation of port 4 ....................................................................................................................... 116
Port 5 ................................................................................................................................................ 117
Registers of the Port 5 (PDR5, DDR5) ........................................................................................ 119
Operation of Port 5 ...................................................................................................................... 121
Port 6 ................................................................................................................................................ 123
Register the Port 6 (PDR6) .......................................................................................................... 125
Operation of port 6 ....................................................................................................................... 127
Port 7 ................................................................................................................................................ 128
Registers of Port 7 (PDR7, DDR7) .............................................................................................. 130
Operation of Port 7 ...................................................................................................................... 132
CHAPTER 5
5.1
5.2
TIMEBASE TIMER .................................................................................... 159
Overview of the Timebase Timer ...................................................................................................... 160
Configuration of the Timebase Timer ................................................................................................ 162