參數(shù)資料
型號(hào): MAXQ610J-0000+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 12 MHz, RISC MICROCONTROLLER, QCC44
封裝: ROHS COMPLIANT, TQFN-44
文件頁(yè)數(shù): 26/29頁(yè)
文件大?。?/td> 827K
代理商: MAXQ610J-0000+
MAXQ610
16-Bit Microcontroller with Infrared Module
6
_______________________________________________________________________________________
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0°C to +70°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
WAKE-UP TIMER
Wake-Up Timer Interval
tWAKEUP
1/fNANO
65,535/
fNANO
s
FLASH MEMORY
System Clock During Flash
Programming/Erase
fFPSYSCLK
6
MHz
tME
Mass erase
20
40
Flash Erase Time
tERASE
Page erase
20
40
ms
Flash Programming Time per
Word
tPROG
(Note 11)
20
100
μs
Write/Erase Cycles
20,000
Cycles
Data Retention
TA = +25°C
100
Years
IR
Carrier Frequency
fIR
(Note 5)
fCK/2
Hz
Note 1:
Specifications to 0°C are guaranteed by design and are not production tested.
Note 2:
It is not recommended to write to flash memory when the supply voltage drops below the power-fail warning levels as
there is uncertainty in the duration of continuous power supply. The user application should check the status of the power-
fail warning flag before writing to flash to ensure complete write operations.
Note 3:
The power-fail warning monitor and the power-fail reset monitor track each other with a minimum delta between the two of
0.11V.
Note 4:
The power-fail reset and power-on-reset (POR) detectors operate in tandem to ensure that one or both signals are active
at all times when VDD < VRST. Doing so ensures the device maintains the reset state until the minimum operating voltage is
achieved.
Note 5:
Guaranteed by design and not production tested.
Note 6:
Measured on the VDD pin and the part not in reset. All inputs are connected to GND or VDD. Outputs do not source/sink
any current. Part is executing code from flash memory.
Note 7:
The power-check interval (PCI) can be set to always on, 1024, 2048, or 4096 nanopower ring oscillator clock cycles.
Note 8:
Current consumption during POR when powering up while VDD < VPOR.
Note 9:
The minimum amount of time that VDD must be below VPFW before a power-fail event is detected.
Note 10: The maximum total current, IOH (max) and IOL (max), for all listed outputs combined should not exceed 32mA to satisfy
the maximum specified voltage drop. This does not include the IRTX output.
Note 11: Programming time does not include overhead associated with utility ROM interface.
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